IP Library Granted Patent US 12,417,043
Granted Patent B2
US 12,417,043 · App. 18/448,887 · Granted Sep 16, 2025

Selectable performance boost for storage devices

Inventors: Ramanathan Muthiah (Bangalore, IN); Taninder Singh Sijher (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/064G06F3/0607G06F3/0679
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Quick Facts
Patent No.
US 12,417,043
App. No.
18/448,887
Granted
Sep 16, 2025
Kind
B2
Abstract

A data storage device is configured to boost either capacity or performance using a set of reserve memory blocks. The data storage device includes a storage media and control circuitry. The storage media includes first set of memory blocks at a first capacity level and a first performance level and a reserve set of memory blocks. The control circuitry is configured to, in response to receiving a selection of a first storage mode from a user, allocate the reserve set of memory blocks to provide a second performance level greater than the first performance level. The control circuitry is further configured to, in response to receiving a selection of a second storage mode from the user, allocate the reserve set of memory blocks to provide a second capacity level greater than the first capacity level.

Claims (60)

1. A data storage device comprising:

storage media comprising:

a first set of memory blocks at a first capacity level and a first performance level; and

a reserve set of memory blocks; and

control circuitry configured to:

in response to receiving a first selection associated with a first storage mode from a user, allocate the reserve set of memory blocks to provide a second performance level greater than the first performance level, wherein the second performance level comprises at least one of faster write speed and greater endurance in comparison to the first performance level;

in response to receiving a second selection associated with a second storage mode from the user, allocate the reserve set of memory blocks to provide a second capacity level greater than the first capacity level; and

in response to receiving a third selection associated with a third storage mode from the user, allocate the reserve set of memory blocks to provide a third performance level and a third capacity to either balance or prioritize performance or capacity based on a ratio indicated by a user using an open sliding scale.

2. The data storage device of claim 1 , wherein the reserve set of memory blocks comprises hybrid memory cells configured to operate in either single-level cell (SLC) mode or multi-level cell (MLC) mode.

3. The data storage device of claim 2 , wherein:

allocating the reserve set of memory blocks to provide the second performance level comprises configuring the hybrid memory cells to operate in SLC mode; and

allocating the reserve set of memory blocks to provide the second capacity level comprises configuring the hybrid memory cells to operate in MLC mode.

4. The data storage device of claim 1 , the data storage device further comprising a fingerprint sensor formed on an external surface of an enclosure of the data storage device.

5. The data storage device of claim 4 , wherein receiving the selection of the first storage mode from the user comprises:

receiving a first fingerprint on the fingerprint sensor; and

determining that the first fingerprint is associated with the first storage mode.

6. The data storage device of claim 5 , wherein receiving the selection of the second storage mode from the user comprises:

receiving a second fingerprint on the fingerprint sensor; and

determining that the second fingerprint is associated with the second storage mode.

7. The data storage device of claim 1 , wherein:

receiving the selection of the first storage mode from the user comprises receiving, on a user interface associated with the data storage device, the selection of the first storage mode; and

receiving the selection of the second storage mode from the user comprises receiving, on the user interface associated with the data storage device, the selection of the second storage mode.

8. The data storage device of claim 1 , the data storage device further comprising a communication port configured to be physically connected to a host system.

9. The data storage device of claim 8 , wherein the communication port comprises a universal serial bus (USB) port that is further configured to provide power to the data storage device.

10. The data storage device of claim 1 , wherein the data storage device is a solid state drive (SSD) and the reserve set of memory blocks comprise overprovisioned memory blocks.

11. The data storage device of claim 1 , further comprising one or more light emitting diodes (LEDs), the control circuitry further configured to:

indicate the first storage mode is active by causing the one or more LEDs to display a first color; and

indicate the second storage mode is active by causing the one or more LEDs to display a second color.

12. A method for boosting either capacity or performance of a data storage device, the method comprising:

initializing a connection between a host system and a data storage device, the data storage device comprising a reserve set of memory blocks and a first set of memory blocks at a first capacity level and a first performance level;

in response to receiving a first selection associated with a first storage mode from a user, allocating the reserve set of memory blocks to provide a second performance level greater than the first performance level, wherein the second performance level comprises at least one of faster write speed and greater endurance in comparison to the first performance level;

in response to receiving a second selection associated with a second storage mode from the user, allocating the reserve set of memory blocks to provide a second capacity level greater than the first capacity level; and

in response to receiving a third selection associated with a third storage mode from the user, allocate the reserve set of memory blocks to provide a third performance level and a third capacity to either balance or prioritize performance or capacity based on a ratio indicated by a user using an open sliding scale.

13. The method of claim 12 , wherein the reserve set of memory blocks comprises hybrid memory cells configured to operate in either single-level cell (SLC) mode or multi-level cell (MLC) mode.

14. The method of claim 13 , wherein:

allocating the reserve set of memory blocks to provide the second performance level comprises configuring the hybrid memory cells to operate in SLC mode; and

allocating the reserve set of memory blocks to provide the second capacity level comprises configuring the hybrid memory cells to operate in MLC mode.

15. The method of claim 13 , wherein:

the data storage device further comprises a fingerprint sensor formed on an external surface of an enclosure of the data storage device; and

receiving the selection of the first storage mode from the user comprises:

receiving a first fingerprint on the fingerprint sensor; and

determining that the first fingerprint is associated with the first storage mode.

16. The method of claim 15 , wherein receiving the selection of the second storage mode from the user comprises:

receiving a second fingerprint on the fingerprint sensor; and

determining that the second fingerprint is associated with the second storage mode.

17. The method of claim 12 , wherein:

receiving the selection of the first storage mode from the user comprises receiving, on a user interface associated with the data storage device, the selection of the first storage mode; and

receiving the selection of the second storage mode from the user comprises receiving, on the user interface associated with the data storage device, the selection of the second storage mode.

18. The method of claim 12 , further comprising:

indicating the first storage mode is active by causing one or more light emitting diodes (LEDs) of the data storage device to display a first color; and

indicating the second storage mode is active by causing the one or more LEDs to display a second color.

19. A data storage device comprising:

means for storing data comprising:

a first set of memory blocks at a first capacity level and a first performance level; and

a reserve set of memory blocks;

means for receiving a selection of a storage mode of a plurality of storage modes from a user; and

control circuitry configured to:

in response to receiving the selection of a first storage mode of the plurality of storage modes, allocate the reserve set of memory blocks to provide a second performance level greater than the first performance level, wherein the second performance level comprises at least one of faster write speed and greater endurance in comparison to the first performance level;

in response to receiving the selection of a second storage mode of the plurality of storage modes, allocate the reserve set of memory blocks to provide a second capacity level greater than the first capacity level; and

in response to receiving the selection of a third storage mode of the plurality of storage modes from the user, allocate the reserve set of memory blocks to provide a third performance level and a third capacity to either balance or prioritize performance or capacity based on a ratio indicated by a user using an open sliding scale.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2023
From: MUTHIAH, RAMANATHAN; SIJHER, TANINDER SINGH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064596/0313 →
Continuity (2)
Provisional Application 63521851 · Jun 19, 2023
Related Publication 20240419348A1 · Dec 19, 2024
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