Combined semiconductor device packaging system
A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package. The combined semiconductor device package may be used for packaging a memory device that allows for increased memory package without increasing the package form factor.
1. A combined semiconductor device package comprising:
a first semiconductor device package comprising:
a first semiconductor chip housed within a first enclosure;
a first substrate coupled to the first enclosure on a first side of the first substrate, the first substrate including a first plurality of solder balls and a second plurality of solder balls, the first plurality of solder balls and the second plurality of solder balls each in electrical communication with the first semiconductor chip; and
a plurality of conductive pads directly coupled to the first substrate on a second side of the first substrate, the second side opposite the first side of the first substrate, the plurality of conductive pads in electrical communication with the first plurality of solder balls and the second plurality of solder balls;
a second semiconductor device package comprising:
a second semiconductor chip housed within a second enclosure; and
a third plurality of solder balls in electrical communication with the second semiconductor chip, the third plurality of solder balls coupled to the plurality of conductive pads of the first semiconductor device package; and
a second substrate including an opening,
wherein the first and second semiconductor device packages are configured to couple to the second substrate, the second enclosure being sized to extend through the opening in the second substrate.
2. The combined semiconductor device package of claim 1 , wherein the first substrate is configured to electrically couple each of the first semiconductor chip and the second semiconductor chip to the first plurality of solder balls and the second plurality of solder balls.
3. The combined semiconductor device package of claim 1 , wherein the first plurality of solder balls and the second plurality of solder balls are positioned opposite regions about the first enclosure.
4. The combined semiconductor device package of claim 1 , wherein the plurality of conductive pads is positioned between the first plurality of solder balls and the second plurality of solder balls of the first substrate.
5. The combined semiconductor device package of claim 1 , wherein the first plurality of solder balls of the first substrate and second plurality of solder balls of the first substrate are configured to electrically couple the first semiconductor device package and the second semiconductor device package to the second substrate.
6. The combined semiconductor device package of claim 1 , wherein the first substrate includes a plurality of connecting elements electrically coupling the first semiconductor chip of the first semiconductor device package and the plurality of conductive pads of the first semiconductor device package to the first plurality of solder balls and the second plurality of solder balls of the first substrate.
7. The combined semiconductor device package of claim 1 , wherein the first substrate includes an inner portion positioned between the first enclosure of the first semiconductor device package and the plurality of conductive pads, and an outer portion extending around an outer edge of the inner portion and integrally formed with the inner portion.
8. The combined semiconductor device package of claim 7 , wherein the inner portion has a thickness which is less than a thickness of the outer portion.
9. The combined semiconductor device package of claim 1 , wherein the first enclosure of the first semiconductor device package and the second enclosure of the second semiconductor device package have generally the same width.
10. A combined semiconductor device package comprising:
first package means for electrically coupling one or more storage means comprising:
first enclosure means for housing a first storage means for providing a first data storage capacity;
first substrate means for providing electrical communication to the first storage means, the first substrate means directly coupled to the first enclosure means and including a first contact means for transmitting to and receiving electrical signals from the first storage means, the first contact means in electrical communication with the first substrate means; and
second contact means for providing electrical communication to the first contact means, the second contact means coupled to the first substrate means opposite the first enclosure means;
second package means for providing a second storage means for providing a second data storage capacity, the second package means comprising:
second enclosure means for housing the second storage means; and
third contact means for providing electrical communication to the second storage means, the third contact means electrically coupled to the second contact means such that the second storage means is in electrical communication with the first substrate means; and
a second substrate means for providing electrical communication to the first substrate means, the second substrate means including an opening,
wherein the first and second package means is configured to couple to the second substrate means, the second enclosure means being sized to extend through the opening in the second substrate means.
11. The combined semiconductor device package of claim 10 , wherein the first substrate means is configured to couple the first package means to the second substrate means.
12. The combined semiconductor device package of claim 11 , wherein the second substrate means includes one or more receiving means configured to receive at least one of the first packaging means and the second packaging means.
13. A semiconductor device comprising:
a combined semiconductor device package comprising:
a first semiconductor device package comprising:
a first semiconductor chip housed within a first enclosure;
a first substrate coupled to the first enclosure on a first side of the first substrate, the first substrate including a first plurality of solder balls and a second plurality of solder balls, the first plurality of solder balls and the second plurality of solder balls each in electrical communication with the first semiconductor chip; and
a plurality of conductive pads directly coupled to the first substrate on a second side of the first substrate, the second side opposite the first side of the first substrate, the plurality of conductive pads in electrical communication with the first plurality of solder balls and the second plurality of solder balls; and
a second semiconductor device package comprising:
a second semiconductor chip housed within a second enclosure; and
a third plurality of solder balls in electrical communication with the second semiconductor chip, the third plurality of solder balls coupled to the plurality of conductive pads of the first semiconductor device package; and
a second substrate having a top surface, a bottom surface opposite the top surface, and one or more openings extending from the top surface to the bottom surface,
wherein the first plurality of solder balls and the second plurality of solder balls are coupled to the second substrate, and the second enclosure extends at least partially through a first opening of the one or more openings in the second substrate.
14. The semiconductor device of claim 13 , wherein the first substrate is configured to electrically couple the first semiconductor chip of the first semiconductor device package and the second semiconductor chip of the second semiconductor device package to the first plurality of solder balls and the second plurality of solder balls of the first semiconductor device package.
15. The semiconductor device of claim 13 , wherein the plurality of conductive pads is positioned between the first plurality of solder balls and the second plurality of solder balls.
16. The semiconductor device of claim 13 , wherein the first substrate includes an inner portion positioned between the first enclosure and the plurality of conductive pads, and an outer portion extending around an outer edge of the inner portion and integrally formed with the inner portion.
17. The semiconductor device of claim 16 , wherein the first plurality of solder balls and second plurality of solder balls of the first semiconductor device package are coupled to the outer portion of the first substrate opposite one another.
18. The semiconductor device of claim 16 , wherein the inner portion of the first substrate has a thickness which is less than a thickness of the outer portion of the first substrate.
19. The semiconductor device of claim 13 , wherein the second substrate further includes a first plurality of conductive pads configured to electrically couple to the first plurality of solder balls of the first semiconductor device package, and a second plurality of conductive pads configured to electrically couple to the second plurality of solder balls of the first semiconductor device package, the first plurality of conductive pads positioned proximate a first side of the first opening of the one or more openings and the second plurality of conductive pads positioned proximate a second side of the first opening opposite the first side.