Configurable neural network engine for convolutional filter sizes
Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units (“DPUs”) that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.
1. A device for performing computations of a convolutional neural network, the device comprising:
a processing chip including:
a first arrangement of a plurality of tensor arrays including circuitry configured for performing computations according to a default convolutional filter size;
a second arrangement of a plurality of memory cells configured to store outputs of corresponding tensor arrays;
a plurality of intra-element buses, each intra-element bus connecting a tensor array to a memory cell to form a core;
a plurality of inter-element buses, each inter-element bus connecting at least two cores;
a computer-readable memory storing instructions for configuring the processing chip to perform computations of the convolutional neural network; and
a controller configured by the instructions to:
determine, for a particular convolution of a convolutional layer of the convolutional neural network, a particular convolutional filter size used for the particular convolution;
when the particular convolutional filter size equals the default convolutional filter size, configure a processing unit to include one of the tensor arrays, and configure the processing unit to perform the particular convolution using the default convolutional filter size;
when the particular convolutional filter size is less than the default convolutional filter size, configure the processing unit to include one of the tensor arrays, and configure the processing unit to perform the particular convolution using the default convolutional filter size padded with zeros such that a padded portion with an unpadded portion of the default convolutional filter corresponds to the particular convolutional filter size; and
in response to the particular convolutional filter size being greater than the default convolutional filter size, configure the processing unit to include multiple tensor arrays from different cores and less than all the memory cells of the different cores to perform the particular convolution, wherein the outputs of the tensor arrays included in the processing unit are sent to the memory cell or memory cells included in the processing unit.
2. The device of claim 1 , wherein the default convolutional filter size is 5×5×1.
3. The device of claim 1 , wherein the device is configured to:
provide input into the processing chip for the processing chip to perform the particular convolution using the processing unit; and
provide an output of the processing chip as an output of the convolutional neural network.
4. The device of claim 1 , wherein the controller is further configured by the instructions to configure a particular tensor array to perform a weighting of a fully connected layer of the convolutional neural network by instructing the tensor array to use a center value of the default convolutional filter for weighting input data and pad remaining values of the default convolutional filter with zeros.
5. The device of claim 1 , wherein at least one tensor array of the plurality of tensor arrays includes circuitry to perform a single multiplication operation.
6. The device of claim 1 , wherein at least one tensor array of the plurality of tensor arrays includes circuitry to perform a plurality of multiplication operations.
7. The device of claim 1 , wherein the controller is further configured by the instructions to configure the processing chip into a plurality of processing units that collectively perform the computations of multiple layers of the convolutional neural network.
8. The device of claim 7 , wherein the plurality of processing units form an array, wherein the array comprises a plurality of systolic transfer structures to systolically transfer outputs generated by a first subset of the processing units for one layer of the convolutional neural network to a second subset of processing units assigned to a next layer of the convolutional neural network.
9. A method for performing computations of a neural network, the method comprising:
identifying a default filter size of a plurality of tensor arrays included in a processing chip, wherein the processing chip further includes:
a plurality of intra-element buses, each intra-element bus connecting a tensor array to a memory cell to form a core; and
a plurality of inter-element buses, each inter-element bus connecting at least two cores;
determining, for a particular convolution of a layer of the neural network, a particular filter size used for the particular convolution;
determining that the particular filter size is greater than the default filter size; and
in response to determining that the particular filter size is greater than the default filter size, configuring a processing unit to include multiple tensor arrays from different cores and less than all the memory cells within the different cores to perform the particular convolution, wherein the outputs of the tensor arrays of the processing unit are sent to the memory cell or memory cells included in the processing unit.
10. The method of claim 9 , wherein the default filter size is 5×5×1.
11. The method of claim 9 , wherein the method further comprises:
providing input into the processing chip for the processing chip to perform the particular convolution using the processing unit; and
providing an output of the processing chip as an output of the neural network.
12. The method of claim 9 , wherein the method further comprises configuring a particular tensor array to perform a weighting of a fully connected layer of the neural network by instructing the tensor array to use a center value of the default filter for weighting input data and padding remaining values of the default filter with zeros.
13. The method of claim 9 , wherein at least one tensor array of the plurality of tensor arrays includes circuitry to perform a single multiplication operation.
14. The method of claim 9 , wherein at least one tensor array of the plurality of tensor arrays includes circuitry to perform a plurality of multiplication operations.
15. The method of claim 9 , wherein the method further comprises configuring the processing chip into a plurality of processing units that collectively perform the computations of multiple layers of the neural network.
16. The method of claim 15 , wherein the plurality of processing units form an array, wherein the array comprises a plurality of systolic transfer structures to systolically transfer outputs generated by a first subset of the processing units for one layer of the neural network to a second subset of processing units assigned to a next layer of the neural network.
17. A controller comprising one or more processors configured to:
identify a default filter size of a plurality of tensor arrays included in a processing chip, wherein the processing chip further includes:
a plurality of intra-element buses, each intra-element bus connecting a tensor array to a memory cell to form a core; and
a plurality of inter-element buses, each inter-element bus connecting at least two cores;
determine, for a particular convolution, of a layer of a neural network, a particular filter size used for the particular convolution;
when the particular filter size equals the default filter size, configure a processing unit to include one of the tensor arrays, and configure the processing unit to perform the particular convolution using the default filter size;
when the particular filter size is less than the default filter size, configure the processing unit to include one of the tensor arrays, and configure the processing unit to perform the particular convolution using the default filter size padded with zeros such that an unpadded portion of the default filter corresponds to the particular filter size; and
in response to the particular filter size being greater than the default filter size, configure the processing unit to include multiple tensor arrays from different cores and less than all the memory cells of the different cores to perform the particular convolution wherein the outputs of the tensor arrays of the processing unit are sent to the memory cell or memory cells included in the processing unit.
18. The controller of claim 17 , wherein the default filter size is 5×5×1.
19. The controller of claim 17 , wherein the one or more processors are further configured to:
provide input into the processing chip for the processing chip to perform the particular convolution using the processing unit; and
provide an output of the processing chip as an output of the neural network.
20. The controller of claim 17 , wherein the one or more processors are further configured for a particular tensor array to perform a weighting of a fully connected layer of the neural network by instructing the tensor array to use a center value of the default filter for weighting input data and padding remaining values of the default filter with zeros, wherein the controller performs the weighting by computer executable instructions stored in a non-transitory computer-readable medium.