Sideband information over host interface considering link states
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L 0 , retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
create one or more thresholds for sending sideband information to a host device, wherein the one or more thresholds correspond to a link state between the host device and the data storage device, wherein the one or more thresholds are based on a time of retaining sideband information, wherein the controller utilizes a plurality of timers with each timinq different sideband information;
determine that link state is in a state other than L 0 ;
retain the sideband information until the one or more thresholds is reached; and
send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state.
2. The data storage device of claim 1 , wherein an L 0 s state is associated with a first threshold, and wherein the first threshold is greater than a maximum payload size (MPS).
3. The data storage device of claim 2 , wherein an L 1 state is associated with a second threshold, and wherein the second threshold is greater than the first threshold.
4. The data storage device of claim 3 , wherein an L 2 state is associated with a third threshold, and wherein the third threshold is greater than the second threshold.
5. The data storage device of claim 4 , wherein one or more L 1 substates are associated with the third threshold.
6. The data storage device of claim 1 , wherein the sideband information is retained and sent in a first-in first-out (FIFO) order.
7. The data storage device of claim 1 , wherein the sideband information is retained in a buffer.
8. The data storage device of claim 1 , wherein the one or more thresholds comprises a timing threshold.
9. The data storage device of claim 8 , wherein the one or more thresholds further comprises a plurality of retained sideband information thresholds.
10. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
create one or more thresholds for sending sideband information to a host device, wherein the one or more thresholds correspond to a link state between the host device and the data storage device, wherein the one or more thresholds are based on a time of retaininq sideband information:
determine that link state is in a state other than L 0 :
retain the sideband information until the one or more thresholds is reached; and
send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state, wherein the controller is further configured to:
activate a timer when first sideband data is delivered to a buffer;
accumulate additional sideband data in the buffer; and
deliver the accumulated sideband data to the host device upon reaching a timing threshold of the one or more thresholds.
11. The data storage device of claim 10 , wherein the timing threshold is dependent on a link state between the host device and the data storage device, wherein an L 0 s state is associated with a first timing threshold, wherein an L 1 state is associated with a second timing threshold, and wherein the second timing threshold is greater than the first timing threshold.
12. The data storage device of claim 11 , wherein an L 2 state is associated with a third timing threshold, and wherein the third timing threshold is greater than the second timing threshold.
13. The data storage device of claim 12 , wherein one or more L 1 substates are associated with the third timing threshold.
14. The data storage device of claim 13 , wherein a difference in time between the first timing threshold, the second timing threshold, and the third timing threshold is equal.
15. The data storage device of claim 10 , wherein the one or more threshold comprises a plurality of timing thresholds and each of the timing thresholds are equal.
16. The data storage device of claim 10 , wherein the one or more threshold comprises a plurality of timing thresholds and each of the timing thresholds of the plurality of timing thresholds are adjusted dynamically.
17. A data storage device comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
create one or more thresholds for sending sideband information to a host device, wherein the one or more thresholds correspond to a link state between the host device and the data storage device, wherein the one or more thresholds are based on a time of retaining sideband information:
determine that link state is in a state other than L 0 :
retain the sideband information until the one or more thresholds is reached; and
send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state, wherein the controller is further configured to:
accumulate sideband information in a buffer;
wake up a link between the host device and the data storage device; and
send the accumulated sideband information to the host device.
18. The data storage device of claim 17 , wherein each link state has a corresponding threshold of a plurality of thresholds, and wherein a first threshold is less than a second threshold.
19. The data storage device of claim 18 , wherein the first threshold and the second threshold are in a MPS granularity, wherein the first threshold is greater than a first MPS granularity, and wherein the first MPS granularity is equal to a MPS.
20. The data storage device of claim 18 , wherein the corresponding threshold is independent of a timing threshold, and wherein a first timing threshold for a first link state is independent of a second timing threshold for a second link state.