Methods and systems for implementing redundancy in memory controllers
The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
1. A method for one or more memory controllers, the method comprising:
receiving a first data;
storing the first data into a first data memory element, wherein data memory elements comprise the first data memory element and a parity data memory element;
changing a first phase bit corresponding to the first data memory element;
assessing a second phase bit corresponding to the parity data memory element;
when the second phase bit is in an invalid state, storing the first data into the parity data memory element; and
when the second phase bit is in a valid state,
performing a logical operation between the first data and data in the parity data memory element, to produce a first result; and
storing the first result into the parity data memory element.
2. The method of claim 1 , wherein:
changing the first phase bit comprises changing the first phase bit corresponding to the first data memory element, from the invalid state to the valid state; and
when the second phase bit is determined to be in the invalid state, changing the second phase bit from the invalid state to the valid state.
3. The method of claim 1 , wherein data of the first data memory element is restorable from one or more data of the data memory elements in the valid state and data stored in the parity data memory element.
4. The method of claim 1 , wherein the logical operation to produce the first result is an exclusive OR logical operation.
5. The method of claim 1 , wherein data is stored into the parity data memory element incrementally.
6. The method of claim 1 , comprising:
transferring the stored first data from the first data memory element to a corresponding first storage element; and
initializing the first and second phase bits to the invalid state.
7. The method of claim 6 , wherein the corresponding first storage element is a non-volatile memory located in an independent media unit.
8. The method of claim 1 , wherein:
the data memory elements comprise a first row of data memory elements and a second row of data memory elements;
the first row of data memory elements comprises the parity data memory element;
the second row of data memory elements comprises a second parity data memory element;
the parity data memory element is in a first position of the first row of data memory elements;
the second parity data memory elements is in a second position of the second row of data memory elements;
the parity data memory element and the second parity data memory element are in different positions; and
the first position is different from the second position.
9. A storage system, comprising:
data memory elements, comprising a first data memory element and a parity data memory element; and
one or more controllers configured to cause:
receiving a first data;
storing the first data into the first data memory element;
changing a first phase bit corresponding to the first data memory element;
assessing a second phase bit corresponding to the parity data memory element;
when the second phase bit is in an invalid state, storing the first data into the parity data memory element; and
when the second phase bit is in a valid state,
performing a logical operation between the first data and data in the parity data memory element, to produce a first result; and
storing the first result into the parity data memory element.
10. The storage system of claim 9 , wherein:
changing the first phase bit comprises changing the first phase bit corresponding to the first data memory element, from the invalid state to the valid state; and
when the second phase bit is determined to be in the invalid state, changing the second phase bit from the invalid state to the valid state.
11. The storage system of claim 9 , wherein data of the first data memory element is restorable from one or more data of the data memory elements in the valid state and data stored in the parity data memory element.
12. The storage system of claim 9 , wherein the logical operation to produce the first result is an exclusive OR logical operation.
13. The storage system of claim 9 , wherein data is caused to be stored into the parity data memory element incrementally.
14. The storage system of claim 9 , wherein the one or more controllers are configured to cause:
transferring the stored first data from the first data memory element to a corresponding first storage element; and
initializing the first and second phase bits to the invalid state.
15. The storage system of claim 14 , wherein the corresponding first storage element is a non-volatile memory located in a device separate from the one or more controllers.
16. The storage system of claim 9 , wherein:
the data memory elements comprise a first row of data memory elements and a second row of data memory elements;
the first row of data memory elements comprises the parity data memory element;
the second row of data memory elements comprises a second parity data memory element;
the parity data memory element is in a first position of the first row of data memory elements;
the second parity data memory elements is in a second position of the second row of data memory elements;
the parity data memory element and the second parity data memory element are in different positions; and
the first position is different from the second position.
17. An apparatus, comprising:
data memory elements, comprising a first data memory element and a parity data memory element;
means for receiving a first data;
means for storing the first data into the first data memory element;
means for changing a first phase bit corresponding to the first data memory element;
means for assessing a second phase bit corresponding to the parity data memory element;
when the second phase bit is in an invalid state, means for storing the first data into the parity data memory element; and
when the second phase bit is in a valid state,
means for performing a logical operation between the first data and data in the parity data memory element, to produce a first result; and
means for storing the first result into the parity data memory element.
18. The apparatus of claim 17 , wherein:
the means for changing the first phase bit comprises means for changing the first phase bit corresponding to the first data memory element, from the invalid state to the valid state; and
when the second phase bit is determined to be in the invalid state, the apparatus comprises means for changing the second phase bit from the invalid state to the valid state.
19. The apparatus of claim 17 , wherein data of the first data memory element is restorable from one or more data of the data memory elements in the valid state and data stored in the parity data memory element.
20. The apparatus of claim 17 , wherein:
the data memory elements comprise a first row of data memory elements and a second row of data memory elements;
the first row of data memory elements comprises the parity data memory element;
the second row of data memory elements comprises a second parity data memory element;
the parity data memory element is in a first position of the first row of data memory elements;
the second parity data memory elements is in a second position of the second row of data memory elements;
the parity data memory element and the second parity data memory element are in different positions; and
the first position is different from the second position.