Multi-level cell solid state device and method for transferring data between a host and the multi-level cell solid state device
View Patent ↗Systems and methods for storing data in a multi-level cell (MLC) flash memory are disclosed. One such data storage system has a data path with cascaded data access performance, including multiple storage portions having different data access speeds. A cascaded data path enables flash memory data access that has a more graceful degradation instead of an abrupt decrease in performance during operation.
1. A method of operating a solid state device, the method comprising:
storing cold data in a first portion of a non-volatile memory (NVM) using a first number of bits per cell;
storing warm data in a second portion of the NVM using a second number of bits per cell, less than the first number of bits, wherein the warm data has a higher access frequency than the cold data;
storing hot data in a single level cell (SLC) buffer of the NVM, wherein the hot data has a higher access frequency than the warm data;
receiving a command from a host to transfer data between the host and the NVM;
transferring data between the host and the NVM via at least one of the SLC buffer of the NVM or the second portion of the NVM, based on the command; and
dynamically adjusting a size of the second portion of the NVM, comprising:
determining free space in the second portion of the NVM; and
if the free space is less than a predetermined threshold, increasing the size of the second portion of the NVM for storing the warm data.
2. The method of claim 1 ,
wherein the storing the cold data comprises storing 4 bits per cell in the first portion of the NVM using a quad level cell (QLC) mode, and
wherein the storing the warm data comprises storing 3 bits per cell in the second portion of the NVM using a pseudo triple-level cell (pTLC) mode.
3. The method of claim 2 , wherein the using the pTLC mode comprises:
fixing a first plurality of memory blocks of the second portion to operate in the pTLC mode; and
dynamically switching a second plurality of memory blocks of the second portion to operate either in the pTLC mode or the QLC mode.
4. The method of claim 1 , further comprising:
dynamically adjusting a size of the second portion of the NVM relative to a size of the first portion of the NVM.
5. The method of claim 1 , further comprising:
relocating data among the SLC buffer, the first portion of the NVM and the second portion of the NVM, based on an access frequency of the data by the host.
6. The method of claim 5 , wherein the relocating data comprises:
storing most frequently accessed data in the SLC buffer, less frequently accessed data in the second portion of the NVM operated in a pseudo triple-level cell (pTLC) mode, and least frequently accessed data in the first portion of the NVM operated in a quad-level cell (QLC) mode.
7. A solid state device (SSD) comprising:
a non-volatile memory (NVM) comprising a single level cell (SLC) buffer, and
a controller operatively coupled to the NVM;
wherein the controller is configured to:
store cold data in a first portion of NVM using a first number of bits per cell;
store warm data in a second portion of the NVM using a second number of bits per cell, less than the first number of bits, wherein the warm data has a higher access frequency than the cold data;
store hot data in the SLC buffer of the NVM, wherein the hot data has a higher access frequency than the warm data;
receive a command from a host to transfer data between the host and the NVM;
transfer data between the host and the NVM via at least one of the SLC buffer or the second portion of the NVM, based on the command; and
dynamically adjust a size of the second portion of the NVM, comprising:
determining free space in the second portion of the NVM; and
if the free space is less than a predetermined threshold, increasing the size of the second portion of the NVM for storing the warm data.
8. The SSD of claim 7 , wherein the controller is further configured to:
store the cold data using 4 bits per cell in the first portion of the NVM using a quad-level cell (QLC) mode, and
store the warm data using 3 bits per cell in the second portion of the NVM using a pseudo triple-level cell (pTLC) mode.
9. The SSD of claim 8 , wherein the controller is further configured to:
fix a first plurality of memory blocks of the second portion to operate in the pTLC mode; and
dynamically switch a second plurality of memory blocks of the second portion to operate either in the pTLC mode or the QLC mode.
10. The SSD of claim 7 , wherein the controller is further configured to:
dynamically adjust a size of the second portion of the NVM relative to a size of the first portion of the NVM.
11. The SSD of claim 7 , wherein the controller is further configured to:
relocate data among the SLC buffer, the first portion of the NVM and the second portion of the NVM, based on an access frequency of the data by the host.
12. The SSD of claim 11 , wherein the controller is further configured to:
store most frequently accessed data in the SLC buffer, less frequently accessed data in the second portion of the NVM operated in a pseudo triple-level cell (pTLC) mode, and least frequently accessed data in the first portion of the NVM operated in a quad-level cell (QLC) mode.
13. A solid state device (SSD) comprising:
means for accessing a non-volatile memory (NVM) comprising a first portion configured to store cold data using a first number of bits per cell, a second portion configured to store warm data using a second number of bits per cell less than the first number of bits, and a single level cell (SLC) buffer configured to store hot data, wherein the warm data has a higher access frequency than the cold data, and the hot data has a higher access frequency than the warm data;
means for receiving a command from a host to transfer data between the host and the NVM;
means for transferring data between the host and the NVM via at least one of the SLC buffer of the NVM or the second portion of the NVM, based on the command; and
means for dynamically adjusting a size of the second portion of the NVM, comprising:
determining free space in the second portion of the NVM; and
if the free space is less than a predetermined threshold, increasing the size of the second portion of the NVM for storing the warm data.
14. The SSD of claim 13 , wherein the means for accessing the NVM comprises:
means for storing the cold data in the first portion of the NVM in a quad-level cell (QLC) mode storing 4 bits per cell, and
means for storing the warm data in the second portion of the NVM in a pseudo triple-level cell (pTLC) mode storing 3 bits per cell.
15. The SSD of claim 14 , wherein the means for storing the warm data in the second portion of the NVM comprises:
means for fixing a first plurality of memory blocks of the second portion to operate in the pTLC mode; and
means for dynamically switching a second plurality of memory blocks of the second portion to operate between the pTLC mode and the QLC mode.
16. The SSD of claim 13 , further comprising:
means for dynamically adjusting a size of the second portion of the NVM relative to the first portion of the NVM.
17. The SSD of claim 13 , further comprising:
means for relocating data among the SLC buffer, the first portion of the NVM and the second portion of the NVM, based on an access frequency of the data by the host.
18. The SSD of claim 17 , wherein the means for relocating data comprises:
means for storing most frequently accessed data in the SLC buffer, less frequently accessed data in the second portion of the NVM operated in a pseudo triple-level cell (pTLC) mode, and least frequently accessed data in the first portion of the NVM operated in a quad-level cell (QLC) mode.