Systems and methods for managing physical-to- logical address information
A method for managing physical-to-logical address information in a memory system includes determining whether a memory fragment of a memory block is a last memory fragment of the memory block. The method also includes, in response to a determination that the memory fragment is not the last memory fragment of the memory block: performing a write operation on the memory fragment; storing, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and, in response to a determination that the cache is full, writing, to a next memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache.
1. A method for managing physical-to-logical address information in a memory system, the method comprising:
determining whether a memory fragment of a memory block is a last memory fragment of the memory block;
in response to a determination that the memory fragment is not the last memory fragment of the memory block:
performing a write operation on the memory fragment;
storing, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and
in response to a determination that the cache is full, writing, to a next memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache.
2. The method of claim 1 , wherein the physical-to-logical address information stored in the cache includes sequential data.
3. The method of claim 2 , wherein the control metadata includes logical block address information associated with the memory fragments and a run length, in response to the physical-to-logical address information stored in the cache including sequential data.
4. The method of claim 1 , wherein the physical-to-logical address information stored in the cache includes random data.
5. The method of claim 4 , wherein the control metadata includes logical block address information associated with the memory fragments, in response to the physical-to-logical address information stored in the cache includes random data.
6. The method of claim 1 , further comprising, in response to a determination that the memory fragment is the last memory fragment of the memory block, writing, to the memory fragment, control data associated with the physical-to-logical address information stored in the cache.
7. The method of claim 1 , further comprising, storing, in a master table, information indicating the memory block and offset values indicating a location of the control metadata within the memory block.
8. A controller comprising:
a bus interface in communication with one or more memory blocks of a memory system; and
a processor configured to:
determine whether a memory fragment of a memory block is a last memory fragment of the memory block;
in response to a determination that the memory fragment is not the last memory fragment of the memory block:
perform a write operation on the memory fragment;
store, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and
in response to a determination that the cache is full, write, to a next memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache.
9. The controller of claim 8 , wherein the physical-to-logical address information stored in the cache includes sequential data.
10. The controller of claim 9 , wherein the control metadata includes logical block address information associated with the memory fragments and a run length, in response to the physical-to-logical address information stored in the cache including sequential data.
11. The controller of claim 8 , wherein the physical-to-logical address information stored in the cache includes random data.
12. The controller of claim 11 , wherein the control metadata includes logical block address information associated with the memory fragments, in response to the physical-to-logical address information stored in the cache includes random data.
13. The controller of claim 8 , wherein the processor is further configured to, in response to a determination that the memory fragment is the last memory fragment of the memory block, write, to the memory fragment, control data associated with the physical-to-logical address information stored in the cache.
14. The controller of claim 8 , wherein the processor is further configured to store, in a master table, information indicating the memory block and offset values indicating a location of the control metadata within the memory block.
15. A memory management method comprising:
determining whether a memory fragment of a memory block is a last memory fragment of the memory block;
in response to a determination that the memory fragment is not the last memory fragment of the memory block:
performing a write operation on the memory fragment;
storing, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and
in response to a determination that the cache is full, writing, to a memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache;
storing, in a master table, information indicating the memory block and offset values indicating a location of the control metadata within the memory block; and
performing a garbage collection operation on the memory block using the master table and the control metadata stored in the memory block.
16. The method of claim 15 , wherein the physical-to-logical address information stored in the cache includes sequential data.
17. The method of claim 16 , wherein the control metadata includes logical block address information associated with the memory fragments and a run length, in response to the physical-to-logical address information stored in the cache including sequential data.
18. The method of claim 15 , wherein the physical-to-logical address information stored in the cache includes random data.
19. The method of claim 18 , wherein the control metadata includes logical block address information associated with the memory fragments, in response to the physical-to-logical address information stored in the cache includes random data.
20. The method of claim 15 , further comprising, in response to a determination that the memory fragment is the last memory fragment of the memory block, writing, to the memory fragment, control data associated with the physical-to-logical address information stored in the cache.