Controller for quality of service based arbitrations
A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.
1. A device controller for a memory arrangement device, comprising:
an interface module configured to transmit and receive data from at least one memory array of the memory arrangement device;
a host interface module configured to transmit and receive data from a host;
a time stamp arrangement configured to record a time when a command is received from the host through the host interface module, the time stamp arrangement connected to the host interface module;
a command arbitration arrangement connected to the host interface module, the command arbitration arrangement configured to receive commands received by the host interface module and arbitrate an operational order for the received commands; and
a command queueing arrangement connected to the host interface module and the interface module, wherein the command queueing arrangement is configured to accept commands placed in an order by the command arbitration arrangement, wherein the order is based on an estimated time of completion for each of the commands, wherein the estimating comprises:
estimating a time of completion for at least two commands based on a preliminary order of completion for each command;
comparing the estimated time of completion for the at least two commands to a threshold; and
reordering the preliminary order of completion to a final order of completion if the estimated time of completion for the at least two commands exceeds the threshold such that the at least two commands are completed by the threshold in the final order of completion.
2. The device controller of claim 1 , further comprising:
a completion queue manager connected to the host interface module, wherein the completion queue manager is configured to send a notification to the host, through the host interface module of a completed command.
3. The device controller of claim 2 , further comprising:
an error correction arrangement connected to the host interface module, wherein the error correction arrangement is configured to identify and correct errors in data received from the at least one memory array.
4. The device controller of claim 3 , further comprising a direct memory access arrangement.
5. The device controller of claim 4 , further comprising a data transfer scheduler coupled to the direct memory access arrangement.
6. The device controller of claim 1 , further comprising a command scheduler coupled to the command queueing arrangement.
7. The device controller of claim 1 , wherein the controller is configured to receive a submission queue doorbell from the host.
8. The device controller of claim 7 , wherein the controller is configured to store a doorbell timestamp in the time stamp arrangement.
9. The device controller of claim 8 , wherein the controller is configured to determine whether a relevant command has been fetched.
10. The device controller of claim 9 , wherein the controller is configured to attach the doorbell timestamp to the relevant command.
11. The device controller of claim 10 , wherein the controller is configured to collect bit error rate information.
12. The device controller of claim 10 , wherein the controller is configured to estimate command completion time.
13. The device controller of claim 12 , wherein the controller is configured to provide the relevant command a quality of service classification.
14. The device controller of claim 13 , wherein the controller is configured to perform the command.
15. A memory device, comprising:
at least one memory array configured to store data provided to the array;
an interface module configured to transmit and receive data from at least one memory array;
a host interface module configured to transmit and receive data from a host;
a time stamp arrangement configured to record a time when a command is received from the host through the host interface module, the time stamp arrangement connected to the host interface module;
a command arbitration arrangement connected to the host interface module, the command arbitration arrangement configured to receive commands received by the host interface module and arbitrate an operational order for the received commands; and
a command queueing arrangement connected to the host interface module and the interface module, wherein the command queueing arrangement is configured to accept commands placed in an order by the command arbitration arrangement, wherein the order is based on an estimated time of completion for each of the commands, wherein the estimating comprises:
estimating a time of completion for at least two commands based on a preliminary order of completion for each command;
comparing the estimated time of completion for the at least two commands to a threshold; and
reordering the preliminary order of completion to a final order of completion if the estimated time of completion for the at least two commands exceeds the threshold such that the at least two commands are completed by the threshold in the final order of completion.
16. The memory device of claim 15 , wherein the at least one memory array is a non-volatile memory array.
17. The memory device of claim 16 , wherein the non-volatile memory array is a NAND memory array.
18. The memory device of claim 15 , further comprising an error correction module.
19. The memory device of claim 18 , further comprising a command scheduler coupled to the command queueing arrangement.
20. The memory device of claim 19 , further comprising a completion queue manager.