IP Library Granted Patent US 11,614,896
Granted Patent B2
US 11,614,896 · App. 17/396,243 · Granted Mar 28, 2023

UFS out of order hint generation

Inventors: Shay Benisty (Beer Sheva, IL); Amir Segev (Meiter, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/061G06F3/0604G06F3/0611G06F3/0613G06F3/0619G06F3/0655G06F3/0656G06F3/0661G06F3/0679
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Quick Facts
Patent No.
US 11,614,896
App. No.
17/396,243
Granted
Mar 28, 2023
Kind
B2
Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

Claims (44)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, and to operate in a first mode corresponding to a first bit error rate (BER) and a second mode corresponding to a second BER that is greater than the first BER, wherein the controller is further configured to:

operate in the first mode;

provide a hint to the host device, wherein the hint comprises an indication of what order data will be received from the data storage device, wherein the order of the data will be in a different order than a requested order;

after providing the hint, retrieve the data from the memory device;

detect a hint violation due to BER;

reorder the data to match the order provided in the hint;

deliver the data to the host device;

determine that the BER is greater than a predetermine threshold; and

switch to operation in the second mode.

2. The data storage device of claim 1 , wherein the controller is further configured to determine an availability of memory dies of the memory device prior to providing the hint.

3. The data storage device of claim 2 , wherein the hint is based upon the determined availability of the memory dies.

4. The data storage device of claim 1 , wherein the controller is configured to switch back to operation in the first mode upon determining the BER is below the threshold.

5. The data storage device of claim 4 , wherein the controller stores the data that is out of order from the hint in a buffer prior to the reordering.

6. The data storage device of claim 1 , wherein the data is decoded prior to sending to the host device.

7. The data storage device of claim 1 , wherein the hint takes into account logic to physical address translation and memory die mapping.

8. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, and to operate in a first mode corresponding to a first bit error rate (BER) and a second mode corresponding to a second BER that is greater than the first BER, wherein the controller is configured to:

operate in the second mode;

retrieve data from the memory device;

after retrieving the data, provide a hint to the host device, wherein the hint comprises an indication of what order data will be received from the data storage device, wherein the order of the data will be in a different order than a requested order;

deliver the data to the host device;

compare a BER for the delivered data to a threshold;

determine the BER is less than the threshold; and

switch to operation in the first mode.

9. The data storage device of claim 8 , wherein the controller is configured to determine a bit error rate for the data retrieved from each die of the memory device.

10. The data storage device of claim 9 , wherein the first mode comprises delivering a hint to the host device prior to retrieving the data.

11. The data storage device of claim 8 , wherein during operation in the second mode, the data retrieved from the memory device is sent to a decoder, wherein the data is decoded, and wherein any data that needs corrected is corrected prior to providing the hint.

12. The data storage device of claim 11 , wherein data emerges from the decoder in a different order than the data was delivered to the decoder.

13. The data storage device of claim 8 , wherein the hint is embedded in a UFS packet sent to the host device.

14. A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, wherein the controller is configured to:

provide a hint to the host device, wherein the hint comprises an indication of what order data will be received from the data storage device, wherein the order of the data will be in a different order than a requested order;

switch between a first mode and a second mode, wherein the first mode comprises providing the hint prior to retrieving the data from the memory means, and wherein the second mode comprises providing the hint after retrieving the data from the memory means; and

deliver the data to the host device.

15. The data storage device of claim 14 , wherein the controller is configured to operate in the first mode and switch to the second mode upon determining the data has exceeded a bit error rate threshold.

16. The data storage device of claim 15 , wherein the controller is configured to switch back to the first mode upon determining the data is below a bit error rate threshold.

17. The data storage device of claim 14 , wherein the controller is configured to reorder data received from the memory means to match an order of the hint delivered to the host device.

18. The data storage device of claim 14 , wherein the controller switches to the second mode after delivering requested data to the host device.

19. The data storage device of claim 14 , wherein the hint is based upon logical block array ranges.

20. The data storage device of claim 14 , wherein the hint is based upon obtaining a predetermined quality of service (QoS) threshold.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 058426 FRAME 0815 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0679 →
SECURITY INTEREST Recorded Dec 9, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 058426/0815 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2021
From: BENISTY, SHAY; SEGEV, AMIR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 057119/0015 →