Storage system and method for efficient pipeline gap utilization for background operations
View Patent ↗A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.
1. A method for performing a background operation, the method comprising:
performing, in a controller of a storage system, first and second host operations in a pipeline manner using a plurality of hardware stages defined within the controller wherein:
the storage system is in communication with a host, and
the plurality of hardware stages includes a first hardware stage, a second hardware stage, and a third hardware stage; and
performing, in the controller, a background operation using the second hardware stage after the first host operation finishes using the second hardware stage but before the second host operation uses the second hardware stage, wherein the background operation is completed using a portion of the plurality of hardware stages.
2. The method of claim 1 , wherein the background operation is performed using the second hardware stage when the first hardware stage is being used to perform the second host operation.
3. The method of claim 1 further comprising selecting the background operation from a plurality of background operations.
4. The method of claim 3 , wherein the selection is based on at least one of the following: latency time, hardware stages needed, and whether the background operation is suspendable or atomic.
5. The method of claim 1 , wherein the storage system further comprises a three-dimensional memory in communication with the controller.
6. The method of claim 1 , wherein the storage system is embedded in the host.
7. The method of claim 1 , wherein the storage system is removably connected to the host.
8. A storage system comprising:
a memory; and
a controller comprising a plurality of hardware stages including a first hardware stage, a second hardware stage, and a third hardware stage, wherein the controller is configured to,
operate, during a first period of time, the storage system in a high power mode;
perform, during the first period of time, a plurality of host operations and a background operation, wherein the background operation is completed using a portion of the plurality of hardware stages; and
operate, during a second period of time, the storage system in a low-power mode.
9. The storage system of claim 8 , wherein the controller is further configured to:
perform the background operation using only the second hardware stage, and
use the second hardware stage to perform the background operation after a first one of the plurality of host operations finishes using the second hardware stage but before a second one of the plurality of host operations uses the second hardware stage.
10. The storage system of claim 9 , wherein the controller is further configured to:
perform the background operation using the second hardware stage during a subset of the first period of time, and
perform the second one of the plurality of host operations, using the first hardware during the subset of the first period of time.
11. The storage system of claim 8 , wherein the controller is further configured to select the background operation from a plurality of background operations.
12. The storage system of claim 11 , wherein the selection is based on at least one of the following: latency time, hardware stages needed, and whether the background operation is suspendable or atomic.
13. The storage system of claim 8 , wherein the memory comprises a three-dimensional memory.
14. The storage system of claim 8 , wherein the storage system is embedded in a host.
15. The storage system of claim 8 , wherein the storage system is removably connected to a host.
16. A storage system comprising:
a memory;
means for performing first and second host operations in a pipeline manner using a plurality of hardware stages defined within a controller, the hardware stages including a first hardware stage, a second hardware stage, and a third hardware stage,
wherein the storage system is operated in a high power mode when performing first and second host operations, and,
wherein the storage system remains in the high power mode for a period of time following completion of the second host operation, after which the storage system enters a low-power mode; and
means for performing a background operation using the second hardware stage after the first host operation finishes using the second hardware stage but before the second host operation uses the second hardware stage,
wherein the background operation is performed when the storage system is in the high power mode before the second host operation finishes and
wherein the background operation is completed using a portion of the plurality of hardware stages.
17. The storage system of claim 16 further comprising means for selecting the background operation from a plurality of background operations based on at least one of the following: latency time, hardware stages needed, and whether the background operation is suspendable or atomic.
18. The storage system of claim 16 , wherein the memory comprises a three-dimensional memory.
19. The storage system of claim 16 , wherein the storage system is embedded in a host.
20. The storage system of claim 16 , wherein the storage system is removably connected to a host.