Multi-level cell programming using optimized multiphase mapping with balanced gray code
Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
1. A method, wherein a non-transitory machine-readable medium includes instructions thereon that, when executed by a machine, perform the method comprising:
during a first stage, programming a first data portion into memory cells in a first-level cell mode; and
during a second stage, programming data comprising a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode,
wherein the first-level cell mode is for storing a first number of bits per cell, the second-level cell mode is for storing a second number of bits per cell, the second number is greater than the first number, and the first number is greater than one,
wherein widths of state distributions for the memory cells in the first stage are not uniform,
wherein a total number of transition counts for all memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode,
wherein a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference,
wherein the transition count difference is an integer greater than zero, and
wherein a number of transition counts for each page of multiple pages associated with the first stage is different from a number of transition counts for a corresponding page of multiple pages associated with the second stage.
2. The method of claim 1 , comprising retrieving the mapping as a predetermined value stored in a data storage system.
3. The method of claim 1 ,
wherein for the first stage, programming the first data portion into the memory cells in the first-level cell mode causes providing a first set of significant bits for at least multiple pages of the memory cells, across a first voltage distribution having a first set of states, and
wherein for the second stage, programming the data comprising the second data portion into the memory cells in the second-level cell mode causes providing a second set of significant bits for pages corresponding to the at least multiple pages associated with the first stage, across a second voltage distribution having a second set of states.
4. The method of claim 1 ,
wherein the mapping is based on minimizing a voltage change of the memory cells from the first stage to the second stage while maintaining a balanced Gray code for the memory pages in the second-level cell mode, and
wherein minimizing the voltage change comprises:
determining a total voltage change caused by the second stage with respect to all the programming levels in the second-level cell mode;
dividing the total voltage change by the maximum number of programming levels in the second-level cell mode; and
determining that the divided total voltage satisfies a predetermined voltage range.
5. The method of claim 1 , wherein a width of a state distribution in the memory cells during the first stage is different from a sum of widths of corresponding state distributions in the memory cells during the second stage.
6. The method of claim 1 , comprising:
programming the memory cells in the first-level cell mode to provide a first voltage distribution having a first maximum voltage; and
programming the memory cells in the second-level cell mode to provide a second voltage distribution having a second maximum voltage that is greater than the first maximum voltage.
7. A data storage device, comprising:
memory comprising memory cells; and
one or more controllers configured to cause:
during a first stage, programming a first data portion into memory cells in a first-level cell mode; and
during a second stage, programming data comprising a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode,
wherein the first-level cell mode is for storing a first number of bits per cell, the second-level cell mode is for storing a second number of bits per cell, and the second number is greater than the first number,
wherein widths of state distributions for the memory cells in the first stage are not uniform,
wherein a total number of transition counts for all memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode,
wherein a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference,
wherein the transition count difference is an integer greater than zero, and
wherein a number of transition counts for each page of multiple pages associated with the first stage is different from a number of transition counts for a corresponding page of multiple pages associated with the second stage.
8. The data storage device of claim 7 , wherein the one or more controllers are configured to cause: retrieving the mapping as a predetermined value stored in a data storage system.
9. The data storage device of claim 7 ,
wherein for the first stage, programming the first data portion into the memory cells in the first-level cell mode causes providing a first set of significant bits for at least multiple pages of the memory cells, across a first voltage distribution having a first set of states, and
wherein for the second stage, programming the data comprising the second data portion into the memory cells in the second-level cell mode causes providing a second set of significant bits for pages corresponding to the at least multiple pages associated with the first stage, across a second voltage distribution having a second set of states.
10. The data storage device of claim 7 ,
wherein the mapping is based on minimizing a voltage change of the memory cells from the first stage to the second stage while maintaining a balanced Gray code for the memory pages in the second-level cell mode, and
wherein minimizing the voltage change comprises:
determining a total voltage change caused by the second stage with respect to all the programming levels in the second-level cell mode;
dividing the total voltage change by the maximum number of programming levels in the second-level cell mode; and
determining that the divided total voltage satisfies a predetermined voltage range.
11. The data storage device of claim 10 , wherein determining the total voltage change comprises weighting at least one programming level of the programming levels.
12. The data storage device of claim 7 , wherein a width of a state distribution in the memory cells during the first stage is different from a sum of widths of corresponding state distributions in the memory cells during the second stage.
13. The data storage device of claim 7 , wherein the one or more controllers are configured to cause:
programming the memory cells in the first-level cell mode to provide a first voltage distribution having a first maximum voltage; and
programming the memory cells in the second-level cell mode to provide a second voltage distribution having a second maximum voltage that is greater than the first maximum voltage.
14. The data storage device of claim 7 , wherein the one or more controllers are configured to prevent storing the first data portion in a buffer separate from the memory cells.
15. The data storage device of claim 7 , wherein the one or more controllers are configured to cause reading, without performing error correction, at least a subset of the programmed first data portion from the memory cells.
16. An apparatus, comprising:
during a first stage, means for programming a first data portion into memory cells in a first-level cell mode; and
during a second stage, means for programming data comprising a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode,
wherein the first-level cell mode is for storing a first number of bits per cell, the second-level cell mode is for storing a second number of bits per cell, and the second number is greater than the first number,
wherein widths of state distributions for the memory cells in the first stage are not uniform,
wherein a total number of transition counts for all memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode,
wherein a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference,
wherein the transition count difference is an integer greater than zero, and
wherein a number of transition counts for each page of multiple pages associated with the first stage is different from a number of transition counts for a corresponding page of multiple pages associated with the second stage.