Multi-plane memory management
View Patent ↗Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.
1. An apparatus comprising:
a failure detection circuit that detects a failure of a storage element during a multi-plane operation, wherein the failure detection circuit marks multiple planes of the storage element as bad in response to detecting the failure of the storage element, and fewer than the multiple planes of the storage element have the failure;
a test circuit that performs a test on the multiple planes of the storage element; and
a recycle circuit that enables a portion of the multiple planes of the storage element for use in operations in response to the portion of the multiple planes of the storage element passing the test.
2. The apparatus of claim 1 , wherein the test comprises one or more of an erase operation, a program operation, and a read operation.
3. The apparatus of claim 1 , wherein performing the test comprises:
performing an erase operation on a portion of the storage element;
performing a program operation on a successfully erased portion of the storage element; and
performing a read operation on a successfully programmed portion of the storage element.
4. The apparatus of claim 3 , wherein the portion of the storage element enabled by the recycle circuit comprises a successfully read portion of the storage element.
5. The apparatus of claim 3 , wherein passing the test comprises being successfully read.
6. The apparatus of claim 3 , wherein performing the program operation comprises programming the successfully erased portion with a test pattern.
7. The apparatus of claim 1 , wherein the storage element comprises one or more of a word line, a string, and a block.
8. The apparatus of claim 1 , wherein the recycle circuit removes the portion of the storage element from a bad storage element pool and puts the portion of the storage element into a good storage element pool.
9. The apparatus of claim 1 , wherein the storage element comprises a plurality of blocks, and the portion of the storage element comprises one or more blocks of the plurality of blocks, and wherein at least one block of the plurality of blocks remains disabled for use in operations.
10. The apparatus of claim 1 , wherein the storage element is withdrawn from use for operations in response to the failure of the storage element during the operation.
11. A system comprising:
a controller; and
an array of memory devices, wherein the controller is configured to:
identify a failure of a memory device during a multi-plane operation, wherein, in response to identifying the failure of the memory device, multiple planes of the memory device are marked as bad, and fewer than the multiple planes of the memory device have the failure;
perform an erase operation on a plane of the multiple planes of the memory device;
perform a program operation on a successfully erased plane of the memory device; and
enable a successfully programed plane of the memory device for use in operations.
12. The system of claim 11 , wherein the controller is configured to perform a read operation on a successfully programed plane of the memory device.
13. The system of claim 12 , wherein the controller is configured to enable a successfully read plane of the memory device for use in operations.
14. The system of claim 11 , wherein the controller is configured to, in response to identifying the failure of the memory device, remove the memory device from use in operations.
15. The system of claim 14 , wherein the controller is configured to, in response to removing the memory device from use in operations, wait a predetermined period of time prior to performing the erase operation on the plane of the memory device.
16. An apparatus comprising:
means for checking operation of a memory block, the memory block being removed from use in operations in response to a failure of the memory block during a multi-plane operation, wherein the memory block comprises multiple planes, and fewer than the multiple planes of the memory block have the failure; and
means for returning at least a first plane of the memory block for use in operations in response to a successful operation check, wherein a second plane of the memory block remains unused for operations.
17. The apparatus of claim 16 , further comprising means for identifying the memory block for removal from use in operations.
18. The apparatus of claim 16 , further comprising means for determining to check operation of the memory block.
19. The apparatus of claim 1 , wherein the test on the multiple planes of the storage element comprises a single-plane test performed separately on different planes of the multiple planes by the test circuit.
20. The apparatus of claim 16 , wherein the successful operation check comprises a single-plane test performed separately on the first plane and the second plane of the memory block.