IP Library Granted Patent US 11,169,709
Granted Patent B2
US 11,169,709 · App. 16/693,175 · Granted Nov 9, 2021

System and method for adaptive command fetch aggregation

Inventors: Elkana Richter (Tene, IL); Shay Benisty (Be'er Sheva, IL); Klod Assulin (Be'er Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/061G06F3/0659G06F3/0688G06F13/4282G06F2212/7203G06F2212/7208G06F2213/0026
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Quick Facts
Patent No.
US 11,169,709
App. No.
16/693,175
Granted
Nov 9, 2021
Kind
B2
Abstract

Systems and methods for adaptive fetch coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The host device notifies the memory device, via a doorbell update, of commands on the submission queue. Instead of fetching the command responsive to the doorbell update, the memory device may analyze one or more aspects in order to determine whether and how to coalesce fetching of the commands. In this way, the memory device may include the intelligence to coalesce fetching in order to more efficiently fetch the commands from the host device.

Claims (56)

1. A non-volatile memory device, comprising:

a controller, wherein when the controller receives an indication that one or more commands are available for fetching from at least one submission queue, the controller is configured to:

determine processing capacity of at least one of the non-volatile memory device and a host device;

determine, based on the determined processing capacity, whether one or more fetching criteria have been met;

when the one or more fetching criteria has been met, fetch the one or more commands from the at least one submission queue; and

when the one or more fetching criteria has not been met, wait to fetch the one or more commands from the at least one submission queue, and

wherein the one or more fetching criteria is based on busyness of a bus between the host device and the non-volatile memory device.

2. The non-volatile memory device of claim 1 , wherein the controller is configured to determine the processing capacity of the host device based on an interrupt response time of the host device.

3. The non-volatile memory device of claim 1 , wherein the controller is configured to analyze at least one aspect of the host device to determine the one or more fetching criteria.

4. The non-volatile memory device of claim 1 , wherein the one or more fetching criteria include the one or more commands meeting or exceeding a fetching threshold indicative of a number of commands.

5. The non-volatile memory device of claim 1 , wherein the one or more fetching criteria comprises a wait time since a last fetch for commands.

6. The non-volatile memory device of claim 1 , wherein the one or more fetching criteria comprises a number of commands from the at least one submission queue.

7. The non-volatile memory device of claim 1 , wherein prior to receiving the indication from the host device, the controller is configured to:

analyze one or more aspects related to the at least one submission queue, the host device having caused the commands to be stored on the at least one submission queue for the non-volatile memory device to process; and

determine, based on the analysis of the one or more aspects, the one or more fetching criteria, the fetching criteria indicative of when the non-volatile memory device is to fetch commands from the at least one submission queue.

8. The non-volatile memory device of claim 7 , wherein the controller is configured to:

analyze the one or more aspects related to the at least one submission queue by analyzing patterns between different indications from the host device.

9. The non-volatile memory device of claim 7 , wherein the controller is configured to:

analyze the one or more aspects related to the at least one submission queue by analyzing the busyness of the bus between the host device and the non-volatile memory device.

10. The non-volatile memory device of claim 7 wherein the controller is configured to:

in response to receiving the indication from the host device, analyze the one or more aspects and dynamically determine the one or more fetching criteria.

11. A method, comprising:

receiving an indication that one or more commands are available for fetching from at least one submission queue, wherein the one or more commands have been caused to be stored on the at least one submission queue for a memory device to process; and

when the indication is received:

determining, by the memory device, processing capacity of at least one of the memory device and a host device;

accessing, by the memory device, a fetching threshold;

determining, based on the determined processing capacity, whether the fetching threshold is met;

when the fetching threshold is met, fetching the one or more commands from the at least one submission queue; and

when the fetching threshold is not met, waiting to fetch the one or more commands from the at least one submission queue,

wherein the fetching threshold is based on busyness of a bus between the host device and the memory device.

12. The method of claim 11 , wherein determining the processing capacity of the host device is based on an interrupt response time of the host device.

13. The method of claim 11 , wherein:

the fetching threshold is indicative of a number of commands; and

determining whether the fetching threshold is met comprises determining that the one or more commands meets or exceeds the fetching threshold.

14. The method of claim 11 , wherein:

the fetching threshold is indicative of a wait time; and

determining whether the fetching threshold is met comprises determining whether a time since a last fetch for commands is greater than or equal to the fetching threshold.

15. The method of claim 11 , further comprising:

in response to determining the processing capacity is high, dynamically reducing the fetching threshold; and

in response to determining the processing capacity is low, dynamically increasing the fetching threshold.

16. The method of claim 11 , further comprising analyzing at least one aspect of a communication interface between the host device and the memory device to dynamically determine the fetching threshold.

17. A non-volatile memory device, comprising:

means for receiving an indication that one or more commands are available for fetching from at least one submission queue, wherein the one or more commands are to be stored on the at least one submission queue for the non-volatile memory device to process; and

responsive to receiving the indication:

means for determining processing capacity of at least one of the non-volatile memory device and a host device;

means for accessing a fetching threshold;

means for determining whether the fetching threshold is met;

when the fetching threshold is met, means for fetching the one or more commands from the at least one submission queue; and

when the one or more commands available for fetching is greater than or equal to the fetching threshold, means for waiting to fetch the one or more commands from the at least one submission queue,

wherein the fetching threshold is based on busyness of a bus between the host device and the non-volatile memory device.

18. The non-volatile memory device of claim 17 , wherein:

the means for determining processing capacity includes means for determining processing capacity of the host device based on an interrupt response time of the host device.

19. The non-volatile memory device of claim 17 , wherein:

the means for determining whether the fetching threshold is met includes means for determining whether the one or more commands meet or exceed the fetching threshold indicative of a number of commands.

20. The non-volatile memory device of claim 17 , wherein:

the means for determining whether the fetching threshold is met includes means for determining whether a wait time since a last fetch for commands has elapsed.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052025 FRAME 0088 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0699 →
SECURITY INTEREST Recorded Feb 26, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052025/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2019
From: RICHTER, ELKANA; BENISTY, SHAY; ASSULIN, KLOD
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 051253/0504 →