Non-volatile memory with adaptive wear leveling
View Patent ↗A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to remap logical addresses to physical addresses of the set of non-volatile memory cells according to a plurality of placement mappings and to select a new placement mapping from the plurality of placement mappings according to a cost function associated with the new placement mapping.
1. A non-volatile storage apparatus, comprising:
a set of non-volatile memory cells; and
one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to remap logical addresses to physical addresses of the set of non-volatile memory cells according to a plurality of placement mappings and to select a new placement mapping represented by a new bit string from the plurality of placement mappings according to a cost function associated with the new placement mapping, each of the plurality of placement mappings represented by a corresponding bit string, the one or more control circuits configured to perform the remapping by combining an individual bit string with logical addresses in an exclusive OR (XOR) operation to generate corresponding physical addresses such that a change in the bit string swaps pairs of logical addresses between pairs of physical addresses.
2. The non-volatile storage apparatus of claim 1 wherein the cost function is based on at least one of: a media property of physical units in the set of non-volatile memory cells and a logical property of logical data mapped to the set of non-volatile memory cells.
3. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are further configured to record wear for a plurality of units in the set of non-volatile memory cells and the cost function is based on recorded wear values.
4. The non-volatile storage apparatus of claim 3 wherein the cost function represents a number of individual unit remappings between heavily worn units in the set of non-volatile memory cells and the new placement mapping minimizes remappings between heavily worn units.
5. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is represented by a first number of physical addresses and the one or more control circuits are configured to calculate the cost function for only a second number of physical addresses that is less than the first number of physical addresses.
6. The non-volatile storage apparatus of claim 5 wherein the second number of physical addresses includes only heavily worn cells.
7. The non-volatile storage apparatus of claim 1 wherein the cost function is based on a combination of wear of physical units in the set of non-volatile memory cells and frequency of writes of logical data mapped to the set of non-volatile memory cells.
8. The non-volatile storage apparatus of claim 7 wherein the cost function is based on wear of only heavily worn physical units and on frequency of writes of frequently written logical data.
9. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are further configured to move data stored in the set of non-volatile memory cells from a first physical address to a second physical address in response to selection of the new placement mapping.
10. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is formed in a plurality of memory levels disposed above a substrate in a monolithic three-dimensional memory structure.
11. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise Phase Change Memory (PCM) cells, Resistive Random Access Memory (ReRAM) cells, or Magnetoresistive Random Access Memory (MRAM cells).
12. A method, comprising:
identifying a plurality of placement mappings according to a placement mapping scheme, an individual placement mapping indicating a unique logical to physical relationship between a plurality of logical addresses and a plurality of physical addresses in a non-volatile memory, the plurality of placement mappings representing a subset of all possible logical to physical mappings of the plurality of logical addresses and the plurality of physical addresses;
calculating a plurality of cost values associated with the plurality of placement mappings according to a cost function including calculating a number of individual unit remappings from heavily worn units to heavily worn units for each placement mapping, each placement mapping resulting in swapping all logical addresses between pairs of physical addresses;
selecting a new placement mapping according to the plurality of cost values including selecting a placement mapping with a smallest number of remappings from heavily worn units to heavily worn units; and
moving data stored in the non-volatile memory according to the new placement mapping.
13. The method of claim 12 further comprising recording at least one of: a media property of physical units in the non-volatile memory associated with the plurality of physical addresses, and a logical property of logical data associated with the plurality of logical addresses.
14. The method of claim 13 wherein recording a media property of physical units in the non-volatile memory includes marking a subset of physical units in the non-volatile memory as heavily worn.
15. The method of claim 12 further comprising, prior to calculating the plurality of cost values and selecting the new placement mapping according to the plurality of cost values, performing deterministic wear leveling until at least some portions of the non-volatile memory become heavily worn.
16. The method of claim 12 further comprising:
recording wear of physical units in the non-volatile memory;
recording write frequency of logical units of data;
calculating the plurality of cost values associated with the plurality of placement mappings according to the cost function based on recorded wear of the physical units and recorded write frequency of logical units of data; and
selecting the new placement mapping according to the plurality of cost values such that frequently written logical units of data are mapped to less worn physical units and infrequently written logical units of data are mapped to more worn physical units.
17. The method of claim 12 wherein each of the plurality of placement mappings is represented by a bit string, an individual bit string combined with logical addresses in an exclusive OR (XOR) operation to generate a corresponding physical address.
18. The method of claim 12 wherein each of the plurality of physical addresses represents a region in the non-volatile memory and wherein a deterministic wear leveling scheme is independently implemented in each region.
19. A system comprising:
a set of non-volatile memory cells forming a plurality of units, each unit having a physical address;
means for recording wear for at least a subset of the plurality of units; and
means for selecting a placement mapping for the plurality of units from a plurality of placement mappings, each of the plurality of placement mappings represented by a bit string, an individual bit string combined with logical addresses in an exclusive OR (XOR) operation to generate a corresponding physical address such that a change in the bit string swaps pairs of logical addresses between pairs of physical addresses, the placement mapping selected by calculating a number of individual unit remappings from heavily worn units to heavily worn units for each placement mapping and selecting the placement mapping with a smallest number of remappings from heavily worn units to heavily worn units.
20. The system of claim 19 further comprising:
means for moving data stored in the plurality of units according to the placement mapping.