Methods, solid state drive controllers and data storage devices having a runtime variable raid protection scheme
View Patent ↗A data storage device may comprise a flash controller and an array of flash memory devices coupled to the flash controller. The array may comprise a plurality of S-Pages that may each comprise a plurality of F-Pages. In turn, each of the plurality of F-Pages may be configured to store a variable amount of data and a variable amount of error correction code. The flash controller may be configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within one or more F-Pages having the largest amount of data.
1. A solid state drive controller, comprising:
a processor, the processor being configured to couple to an array of flash memory devices, the array comprising a plurality of dies, each die comprising a plurality of flash blocks (F-Blocks), each F-Block comprising a plurality of flash pages (F-Pages), at least some of the F-Page comprising at least one error correcting code page (E-Page), and at least some of the E-Pages comprising a variably-sized error correction code (ECC) portion and a corresponding variably-sized data portion, the variably-sized data portions within one F-Page defining, in the aggregate, an F-Page data portion,
wherein the processor is configured to:
define an S-Page that comprises a plurality of F-Pages from one or more of the plurality of dies;
within the S-Page,
store an E-Page error correction code within the variably-sized ECC portion of each E-Page within the F-Pages to correct an error within the corresponding variably-sized data portion;
designate at least one F-Page having a largest size F-Page data portion among the F-Pages in the S-Page as a Check Page; and
store a cross-F-Page error correction code within the at least one Check Page.
2. The solid state drive controller of claim 1 , wherein the cross-F-Page error correction code comprises a Forward Error Correction (FEC) code.
3. The solid state drive controller of claim 2 , wherein the FEC code comprises a Reed-Solomon code.
4. The solid state drive controller of claim 1 , wherein the E-Page error correction code comprises a Low-Density Parity-Check (LDPC) error correction code.
5. The solid state drive controller of claim 1 , wherein the processor is configured to generate and store the E-Page error correction code at runtime, at a time of generating one of the plurality of E-Pages.
6. The solid state drive controller of claim 1 , wherein the processor is further configured to generate the cross-F-Page error correction code for the S-Page as data is written to the S-Page.
7. The solid state drive controller of claim 1 , wherein the processor is further configured to read data from the S-Page and to skip the at least one F-Page within the S-Page that has been designated as a Check Page.
8. The solid state drive controller of claim 1 , wherein the processor is further configured to:
set a flag in a block information data structure to designate particular F-Pages within an S-Page as being Check Pages; and
consult the block information data structure to determine which of the F-Pages of an S-Page have been designated as Check Pages.
9. The solid state drive controller of claim 1 , wherein the processor is further configured to designate additional F-Pages in the S-Page as Check Pages, depending upon at least one of: (1) a configuration of the array, (2) a performance of the array and (3) a use-profile of predetermined portions of the array.
10. The solid state drive controller of claim 1 , wherein the processor is further configured to designate additional F-Pages as Check Pages in S-Pages storing a predetermined type of information.
11. The solid state drive controller of claim 10 , wherein the predetermined type of information comprises metadata.
12. The solid state drive controller of claim 10 , wherein the predetermined type of information comprises host-indicated data.
13. The solid state drive controller of claim 1 , wherein as between a first S-Page and a second S-Page, the at least one F-Page designated as a Check Page in the first S-Page occupies a comparatively different position within the first S-Page as does the at least one F-Page designated as a Check Page within the second S-Page.
14. The solid state drive controller of claim 1 , wherein the S-Page is a first S-Page and the controller is further configured to define a second S-Page that has a greater number of F-Pages designated as Check Pages than the first S-Page.
15. The solid state drive controller of claim 1 , wherein the processor is further configured to, when writing to an F-Block, determine at least one of:
(1) a strength of E-Page error correction code to generate within the variably-sized ECC portion of each E-Page;
(2) a strength of cross-F-Page error correction code to generate; and
(3) which F-Pages within an S-Page to designate as a Check Page.
16. The solid state drive controller of claim 1 , wherein the processor is further configured to apply the cross-F-Page error correction code when the E-Page error correction code fails to correct an encountered error.
17. A data storage device, comprising:
the controller of claim 1 , and
the array of flash memory devices.
18. A method of controlling a data storage device, the data storage device comprising a processor, the processor being configured to couple to an array of flash memory devices, the array comprising a plurality of dies, each die comprising a plurality of flash blocks (F-Blocks), each F-Block comprising a plurality of flash pages (F-Pages), at least some of the F-Page comprising at least one error correcting code page (E-Page), and at least some of the E-Pages comprising a variably-sized error correction code (ECC) portion and a corresponding variably-sized data portion, the variably-sized data portions within one F-Page defining, in the aggregate, an F-Page data portion, the method comprising:
defining an S-Page that comprises a plurality of F-Pages from one or more of the plurality of dies;
within the S-Page,
storing an E-Page error correction code within the variably-sized ECC portion of each E-Page within the F-Pages to correct an error within the corresponding variably-sized data portion;
designating at least one F-Page having a largest size F-Page data portion among the F-Pages in the S-Page as a Check Page; and
storing a cross-F-Page error correction code within the at least one Check Page.
19. The method of claim 18 , wherein the cross-F-Page error correction code comprises a Forward Error Correction (FEC) code.
20. The method of claim 19 , wherein the FEC code comprises a Reed-Solomon code.
21. The method of claim 18 , wherein the E-Page error correction code comprises a Low-Density Parity-Check (LDPC) error correction code.
22. The method of claim 18 , wherein storing the E-Page error correction code comprises generating and storing the E-Page error correction code at runtime, at a time of generating one of the plurality of E-Pages.
23. The method of claim 18 , wherein storing the cross-F-Page error correction code comprises generating and storing the cross-F-Page error correction code for the S-Page as data is written to the S-Page.
24. The method of claim 18 , further comprising reading data from the S-Page and skipping the at least one F-Page within the S-Page having been designated as a Check Page.
25. The method of claim 18 , further comprising:
setting a flag in a block information data structure to designate particular F-Pages within an S-Page as being Check Pages; and
consulting the block information data structure to determine which of the F-Pages of an S-Page have been designated as Check Pages.
26. The method of claim 18 , further comprising designating additional F-Pages in the S-Page as Check Pages, depending upon at least one of: (1) a configuration of the array, (2) a performance of the array and (3) a use-profile of predetermined portions of the array.
27. The method of claim 18 , further comprising designating additional F-Pages as Check Pages in S-Pages storing a predetermined type of information.
28. The method of claim 27 , wherein the predetermined type of information comprises one of metadata and host-indicated data.
29. The method of claim 18 , wherein as between a first S-Page and a second S-Page, the at least one F-Page designated as a Check Page in the first S-Page occupies a comparatively different position within the first S-Page as does the at least one F-Page designated as a Check Page within the second S-Page.
30. The method of claim 18 , wherein the S-Page is a first S-Page and wherein the method further comprises defining a second S-Page that has a greater number of F-Pages designated as Check Pages than the first S-Page.
31. The method of claim 18 wherein, when writing to an F-Block, the method further comprises determining at least one of:
(1) a strength of E-Page error correction code to generate within the variably-sized ECC portion of each E-Page;
(2) a strength of cross-F-Page error correction code to generate; and
(3) which F-Pages within an S-Page to designate as a Check Page.
32. The method of claim 18 , further comprising applying the cross-F-Page error correction code when the E-Page error correction code fails to correct an encountered error.
33. A method of controlling a data storage device, the data storage device comprising a flash controller and an array of flash memory devices coupled to the flash controller, the array comprising a plurality of S-Pages that each comprise a plurality of F-Pages, the method comprising:
storing, in each of the plurality of F-Pages, a variable amount of data and a variable amount of error correction code;
generating an error correction code across each F-Page of an S-Page; and
storing the generated error correction code within at least one F-Page having a largest amount of data.
34. A solid state drive controller, comprising:
a processor, the processor being configured to couple to an array of flash memory devices comprising a plurality of S-Pages that each comprise a plurality of F-Pages, each of the plurality of F-Pages being configured to store a variable amount of data and a variable amount of error correction code;
wherein the processor is configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within at least one F-Page comprising a largest amount of data.
35. A data storage device, comprising:
the controller of claim 34 , and
the array of flash memory devices.