Weighted programming patterns in solid-state data storage systems
View Patent ↗Systems and methods are disclosed for programming data in non-volatile memory arrays. A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller configured to improve data retention or reduce read disturb of at least a portion of the solid-state non-volatile memory at least in part by receiving data to be written to the solid-state non-volatile memory. The controller is further configured to, when a data retention programming mode is set, encode the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a lower voltage level than the second programming state, and write the encoded data to the solid-state non-volatile memory. When a read disturb programming mode is set, the first programming state is associated with a higher voltage level than the second programming state.
1. A data storage device comprising:
a solid-state non-volatile memory including a plurality of memory cells; and
a controller configured to improve data retention of at least a portion of the solid-state non-volatile memory at least in part by:
receiving data to be written to the solid-state non-volatile memory;
when a data retention programming mode is set:
encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a lower voltage level than the second programming state; and
writing the encoded data to the solid-state non-volatile memory.
2. The data storage device of claim 1 , further comprising a data randomizer, wherein the controller is further configured to bypass the data randomizer when the data retention programming mode is set.
3. The data storage device of claim 1 , wherein the controller is further configured to receive a request to set the data retention programming mode from a host device communicatively coupled to the data storage device over an interface.
4. The data storage device of claim 1 , wherein the controller is further configured to:
read at least a portion of data stored in the solid-state non-volatile memory;
encode the at least a portion of data using the programming pattern; and
rewrite the encoded at least a portion of data back to the solid-state non-volatile memory.
5. The data storage device of claim 1 , wherein the controller is further configured to program the plurality of memory cells according to a multi-level cell (MLC) programming scheme, wherein the second programming state corresponds to a highest programming state of the MLC programming scheme.
6. The data storage device of claim 1 , wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a lower voltage level than the first programming state.
7. The data storage device of claim 1 , wherein the controller is further configured to set the data retention programming mode in response to a flush command.
8. The data storage device of claim 1 , wherein the controller is further configured to determine that the data retention programming mode is set when a power-down process is initiated.
9. The data storage device of claim 1 , wherein the controller is further configured to set the data retention programming mode based on a type of the data.
10. The data storage device of claim 1 , wherein the controller is further configured to determine whether the data retention programming mode is set at least in part by determining whether the solid-state non-volatile memory has experienced more than a threshold number of write cycles.
11. The data storage device of claim 1 , wherein the controller is further configured to determine whether the data retention programming mode is set at least in part by determining whether a threshold number of blocks of the solid-state non-volatile memory are available in a free block pool of the solid-state non-volatile memory.
12. A method of programming data in a solid-state non-volatile memory, the method comprising:
receiving data to be written to a solid-state non-volatile memory;
determining whether a data retention programming mode associated with the solid-state non-volatile memory is set; and
when the data retention programming mode is set:
encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a lower programming voltage level than the second programming state; and
writing the encoded data to the solid-state non-volatile memory.
13. The method of claim 12 , further comprising bypassing a data randomizer when the data retention programming mode is set.
14. The method of claim 12 , further comprising receiving a request to set the data retention programming mode from a host device communicatively coupled to a data storage device over an interface, the data storage device comprising the solid-state non-volatile memory.
15. The method of claim 12 , further comprising:
reading at least a portion of data stored in the solid-state non-volatile memory;
encoding the at least a portion of data using the programming pattern; and
writing the encoded at least a portion of data back to the solid-state non-volatile memory.
16. The method of claim 12 , further comprising determining whether the data retention programming mode is set at least in part by determining whether the solid-state non-volatile memory has experienced more than a threshold number of write cycles.
17. The method of claim 12 , further comprising determining whether the data retention programming mode is set at least in part by determining whether a threshold number of blocks of the solid-state non-volatile memory are available in a free block pool of the solid-state non-volatile memory.
18. The method of claim 12 , wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a lower voltage level than the first programming state.
19. A data storage device comprising:
a solid-state non-volatile memory including a plurality of memory cells; and
a controller configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by:
receiving data to be written to the solid-state non-volatile memory;
when a read disturb programming mode is set:
encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state; and
writing the encoded data to the solid-state non-volatile memory.
20. The data storage device of claim 19 , further comprising a data randomizer, wherein the controller is further configured to bypass the data randomizer when the read disturb programming mode is set.
21. The data storage device of claim 19 , wherein the controller is further configured to receive a request to set the read disturb programming mode from a host device communicatively coupled to the data storage device over an interface.
22. The data storage device of claim 19 , wherein the controller is further configured to:
read at least a portion of data stored in the solid-state non-volatile memory;
encode the at least a portion of data using the programming pattern; and
rewrite the encoded at least a portion of data back to the solid-state non-volatile memory.
23. The data storage device of claim 19 , wherein the controller is further configured to program the plurality of memory cells according to a multi-level cell (MLC) programming scheme, wherein the second programming state corresponds to a lowest programming state of the MLC programming scheme.
24. The data storage device of claim 19 , wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a higher voltage level than the first programming state.
25. The data storage device of claim 19 , wherein the controller is further configured to set the read disturb programming mode based on a type of the data.
26. The data storage device of claim 19 , wherein the controller is further configured to determine whether the read disturb programming mode is set at least in part by determining whether the solid-state non-volatile memory has experienced more than a threshold number of read or write cycles.