Dynamic calibration of frequency and power storage interface
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.
1. A method, comprising:
determining initial values of a memory interface of a data storage device, wherein the initial values include a minimum write frequency, a minimum read frequency, a maximum write frequency and a maximum read frequency;
receiving an input trigger;
adjusting frequency and voltage of the memory interface, wherein the adjusting comprises:
performing a first operation at a first frequency to determine a first data pattern;
performing a second operation at a second frequency to determine a second data pattern;
determining whether the first pattern equals the second data pattern; and
adjusting the first frequency in response to the determining whether the first data pattern equals the second data pattern, wherein the first frequency is increased when the first data pattern equals the second data pattern, and wherein the first frequency is decreased when the first data pattern is not equal to the second data pattern;
calibrating the frequency to obtain a maximum possible frequency for the memory interface; and
checking a transmitted pattern across the memory interface for errors.
2. The method of claim 1 , wherein the input trigger is selected from the group consisting of: host configuration information, host platform information, data storage device internal inputs, device lifetime information, device temperature, voltage, and combinations thereof.
3. The method of claim 1 , wherein the initial values of the memory interface comply with a maximum read and write power that can be consumed by the memory interface.
4. The method of claim 1 , wherein checking for errors includes read-write comparing.
5. The method of claim 1 , wherein checking for errors includes ensuring a number of errors is below a predefined threshold.
6. The method of claim 1 , further comprising:
receiving a new input trigger; and
repeating the adjusting, calibrating and checking.
7. The method of claim 1 , wherein adjusting the frequency comprises increasing the frequency.
8. The method of claim 7 , wherein adjusting the voltage comprises decreasing the voltage.
9. A method, comprising:
determining initial values of a memory interface of a data storage device, wherein the initial values include a minimum write frequency, a minimum read frequency, a maximum write frequency and a maximum read frequency;
decreasing or increasing the frequency of the memory interface, wherein the decreasing or increasing comprises:
performing a first operation at a first frequency to determine a first data pattern;
performing a second operation at a second frequency to determine a second data pattern;
determining whether the first pattern equals the second data pattern; and
adjusting the first frequency in response to the determining whether the first data pattern equals the second data pattern, wherein the first frequency is increased when the first data pattern equals the second data pattern, and wherein the first frequency is decreased when the first data pattern is not equal to the second data pattern;
increasing voltage to the memory interface; and
repeating the determining, decreasing and increasing while ensuring a number of errors observed remains below a predefined threshold.
10. The method of claim 9 , further comprising:
receiving information regarding host device bus mode configuration or host device power class configuration, wherein the receiving occurs prior to decreasing the frequency.
11. The method of claim 9 , further comprising:
receiving information regarding host device power specifications or host device power high and low power configurations, wherein the receiving occurs prior to decreasing the frequency.
12. The method of claim 9 , further comprising:
receiving information regarding data storage device bottlenecks or data storage device capacitance, wherein the receiving occurs prior to decreasing the frequency.
13. The method of claim 12 , wherein the data storage device bottlenecks includes information regarding one or more of maximum LDPC decode time, memory device programming time, parallelism, number of FIMs, and memory device state.
14. The method of claim 9 , further comprising:
receiving information data storage device lifetime, wherein the receiving occurs prior to decreasing the frequency.
15. The method of claim 9 , further comprising:
receiving information regarding detected data storage device temperature, wherein the receiving occurs prior to decreasing the frequency.
16. The method of claim 9 , further comprising:
receiving information regarding detected data storage device voltage, wherein the receiving occurs prior to decreasing the frequency.
17. A method, comprising:
a step for adjusting one or more of a frequency of a timing signal or a voltage of a memory interface within a constraint and based upon information received from one or more of an internal inputs monitor, host inputs module, device lifetime monitor, temperature sensor, and voltage sensor;
a step for determining values for maximum read and write frequencies;
a step for determining values for minimum read and write frequencies;
a step for determining maximum power for read and write voltages;
a step for decreasing frequency and increasing voltage;
a step for calibrating maximum frequency for read and write;
a step for checking for errors on one or more transmitted patterns over the memory interface;
a step for determining a first data pattern at a first frequency;
a step for determining a second data pattern at a second frequency;
a step for determining, using the plurality of latches working in conjunction with a controller, whether the first data pattern equals the second data pattern;
a step for increasing the first frequency if the first data pattern equals the second data pattern; and
a step for decreasing the first frequency if the first data pattern does not equal the second data pattern.
18. The method of claim 17 , further comprising a step for adjusting a frequency of the memory interface.
19. The method of claim 18 , further comprising a step for adjusting a voltage of the memory interface.
20. The method of claim 17 , further comprising a step for receiving one or more of the following: host device bus mode configuration, host device power class configuration, host device power specifications, and host device power high and low power configurations.