IP Library Granted Patent US 11,474,709
Granted Patent B2
US 11,474,709 · App. 17/153,713 · Granted Oct 18, 2022

Managing data for a data storage system

Inventors: Kai-Lung Cheng (Irvine, CA); Yun-Tzuo Lai (Irvine, CA); Eugene Lisitsyn (Anaheim, CA); Jerry Lo (Hacienda Heights, CA); Subhash Balakrishna Pillai (Irvine, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0619G06F3/064G06F3/065G06F3/0679G06F12/0246G06F12/0253G06F2212/7201G06F2212/7205G06F2212/7211
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Quick Facts
Patent No.
US 11,474,709
App. No.
17/153,713
Granted
Oct 18, 2022
Kind
B2
Abstract

The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.

Claims (48)

1. A machine-implemented method, comprising:

obtaining a data operation request for data associated with a logical address;

determining a first physical address, in a non-volatile memory, mapped to the logical address, wherein the first physical address is associated with a first set of physical addresses, and wherein the first set of physical addresses is associated with a first indicator value;

determining whether the first physical address is indicated as bad, wherein an indication as bad represents a failed operation;

in response to the first physical address being indicated as bad, maintaining the first indicator value associated with the first set of physical addresses and not updating the first indicator value; and

in response to the first physical address being not indicated as bad, changing the first indicator value associated with the first set of physical addresses and removing a mapping between the logical address and the first physical address.

2. The machine-implemented method of claim 1 , wherein determining whether the first physical address is indicated as bad comprises determining whether the first physical address is indicated as bad based on an indication in a bit mask.

3. The machine-implemented method of claim 2 , comprising verifying a bit corresponding to the first physical address in the bit mask, wherein the first physical address is indicated as bad when the bit is set.

4. The machine-implemented method of claim 3 , comprising setting the bit in the bit mask in response to an error occurring during a read operation to read data written to the first physical address.

5. The machine-implemented method of claim 1 , comprising:

performing a write operation to write data associated with the logical address to a second physical address in the non-volatile memory, wherein the write operation writes metadata comprising the logical address to the second physical address; and

facilitating mapping between the logical address and the second physical address.

6. The machine-implemented method of claim 1 , comprising:

determining that the first indicator value associated with the first set of physical addresses is zero; and

designating the first set of physical addresses for erase operations.

7. The machine-implemented method of claim 1 , wherein the non-volatile memory comprises a plurality of non-volatile memory devices, and wherein the first set of physical addresses comprises a respective physical address in each of the plurality of non-volatile memory devices.

8. A data storage system, comprising:

a non-volatile memory; and

one or more controllers configured to cause:

obtaining a data operation request for data associated with a logical address;

determining a first physical address, in the non-volatile memory, mapped to the logical address, wherein the first physical address is associated with a first set of physical addresses, and wherein the first set of physical addresses is associated with a first indicator value;

determining whether the first physical address is indicated as bad, wherein an indication as bad represents a failed operation;

in response to the first physical address being indicated as bad, maintaining the first indicator value associated with the first set of physical addresses and not updating the first indicator value; and

in response to the first physical address being not indicated as bad, changing the first indicator value associated with the first set of physical addresses and removing a mapping between the logical address and the first physical address.

9. The data storage system of claim 8 , wherein determining whether the first physical address is indicated as bad comprises determining whether the first physical address is indicated as bad based on an indication in a bit mask.

10. The data storage system of claim 9 , wherein the one or more controllers are configured to cause verifying a bit corresponding to the first physical address in the bit mask, wherein the first physical address is indicated as bad when the bit is set.

11. The data storage system of claim 10 , wherein the one or more controllers are configured to cause setting the bit in the bit mask in response to an error occurring during a read operation to read data written to the first physical address.

12. The data storage system of claim 8 , wherein the one or more controllers are configured to cause performing a write operation to write data associated with the logical address to a second physical address in the non-volatile memory, wherein the write operation writes metadata comprising the logical address to the second physical address; and

facilitating mapping between the logical address and the second physical address.

13. The data storage system of claim 8 , wherein the one or more controllers are configured to cause:

determining that the first indicator value associated with the first set of physical addresses is zero; and

designating the first set of physical addresses for erase operations.

14. The data storage system of claim 8 , wherein the non-volatile memory comprises a plurality of non-volatile memory devices, and wherein the first set of physical addresses comprises a respective physical address in each of the plurality of non-volatile memory devices.

15. An apparatus, comprising:

means for obtaining a data operation request for data associated with a logical address;

means for determining a first physical address, in a non-volatile memory, mapped to the logical address, wherein the first physical address is associated with a first set of physical addresses, and wherein the first set of physical addresses is associated with a first indicator value;

means for determining whether the first physical address is indicated as bad, wherein an indication as bad represents a failed operation;

means for, in response to the first physical address being indicated as bad, maintaining the first indicator value associated with the first set of physical addresses and not updating the first indicator value; and

means for, in response to the first physical address being not indicated as bad, changing the first indicator value associated with the first set of physical addresses and removing a mapping between the logical address and the first physical address.

16. The apparatus of claim 15 , wherein the means for determining whether the first physical address is indicated as bad comprises means for determining whether the first physical address is indicated as bad based on an indication in a bit mask.

17. The apparatus of claim 16 , comprising means for verifying a bit corresponding to the first physical address in the bit mask, wherein the first physical address is indicated as bad when the bit is set.

18. The apparatus of claim 17 , comprising means for setting the bit in the bit mask in response to an error occurring during a read operation to read data written to the first physical address.

19. The apparatus of claim 15 , comprising:

means for performing a write operation to write data associated with the logical address to a second physical address in the non-volatile memory, wherein the write operation writes metadata comprising the logical address to the second physical address; and

means for facilitating mapping between the logical address and the second physical address.

20. The apparatus of claim 15 , comprising:

means for detecting that the first indicator value associated with the first set of physical addresses is zero; and

means for selecting the first set of physical addresses for erase operations.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 055404 FRAME 0942 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0407 →
SECURITY INTEREST Recorded Feb 24, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 055404/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2021
From: CHENG, KAI-LUNG; LAI, YUN-TZUO; LISITSYN, EUGENE; LO, JERRY; PILLAI, SUBHASH BALAKRISHNA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055169/0355 →