Storing parity data separate from protected data
View Patent ↗A storage device may include a primary storage array comprising a plurality of memory devices, one or more parity memory devices, and a controller configured to store a block of data. The controller may be configured to store the block of data by at least: writing the block of data to the primary storage array, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices.
1. A non-transitory storage device comprising:
a primary storage array comprising a plurality of non-volatile memory devices;
one or more parity memory devices; and
a controller configured to store a block of data by at least:
writing the block of data to the primary storage array;
determining parity data for the block of data; and
selecting a size of parity data to determine for the block of data; and
when a combined size of the selected size of parity data and the block of data is larger than a size of a page of the primary storage array,
writing at least a portion of the determined parity data to the one or more parity memory devices; and
when the combined size of the selected size of parity data and the block of data is smaller than or equal to the size of a page of the primary storage array,
writing the at least a portion of the determined parity data to the primary storage array.
2. The non-transitory storage device of claim 1 , wherein:
to determine the parity data, the controller is configured to determine first parity data and second parity data for the block of data,
to write the block of data to the primary storage array, the controller is configured to write the block of data and the first parity data to a page of the primary storage array, and
to write the portion of the parity data to the one or more parity devices, the controller is configured to write the second parity data to the one or more parity devices.
3. The non-transitory storage device of claim 1 , wherein the controller is further configured to retrieve the block of data by at least:
reading the block of data from the primary storage array;
reading the parity data from the one or more parity devices; and
verifying the block of data based on the parity data.
4. The non-transitory storage device of claim 1 , wherein the plurality of non-volatile memory devices of the primary storage array comprise a plurality of flash memory devices, and wherein the one or more parity memory devices comprise one or more magnetoresisitve random-access memory (MRAM), phase-change random-access memory (PRAM), or resistive random-access memory (ReRAM) memory devices.
5. A method comprising:
writing, by a controller of a storage device, a block of data to a primary storage array comprising a plurality of non-volatile memory devices;
determining, by the controller, parity data for the block of data;
selecting a size of parity data to determine for the block of data; and
when a combined size of the selected size of parity data and the block of data is larger than a size of a page of the primary storage array,
writing, by the controller, at least a portion of the determined parity data to one or more parity memory devices; and
when the combined size of the selected size of parity data and the block of data is smaller than or equal to the size of a page of the primary storage array,
writing, by the controller, the at least a portion of the determined parity data to the primary storage array.
6. The method of claim 5 , wherein:
determining the parity data comprises determining first parity data and second parity data for the block of data,
writing the block of data to the primary storage array comprises writing the block of data and the first parity data to a page of the primary storage array, and
writing the portion of the parity data to the one or more parity devices comprises writing the second parity data to the one or more parity devices.
7. The method of claim 5 , further comprising retrieving the block of data by at least:
reading the block of data from the primary storage array;
reading the parity data from the one or more parity devices; and
verifying the block of data based on the parity data.
8. The method of claim 5 , wherein the plurality of non-volatile memory devices of the primary storage array comprise a plurality of flash memory devices, and wherein the one or more parity memory devices comprise one or more magnetoresisitve random-access memory (MRAM), phase-change random-access memory (PRAM), or resistive random-access memory (ReRAM) memory devices.
9. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors of a storage device to:
write a block of data to a primary storage array comprising a plurality of non-volatile memory devices;
determine parity data for the block of data;
select a size of parity data to determine for the block of data;
when a combined size of the selected size of parity data and the block of data is larger than a size of a page of the primary storage array,
write at least a portion of the determined parity data to one or more parity memory devices; and
when the combined size of the selected size of parity data and the block of data is smaller than or equal to the size of a page of the primary storage array,
write the at least a portion of the determined parity data to the primary storage array.
10. The non-transitory computer-readable storage medium of claim 9 , wherein:
the instructions that cause the one or more processors to determine the parity data comprise instructions that cause the one or more processors to determine first parity data and second parity data for the block of data,
the instructions that cause the one or more processors to write the block of data to the primary storage array comprise instructions that cause the one or more processors to write the block of data and the first parity data to a page of the primary storage array, and
the instructions that cause the one or more processors to write the portion of the parity data to the one or more parity devices comprise instructions that cause the one or more processors to write the second parity data to the one or more parity devices.
11. A system comprising:
a primary storage array comprising a plurality of non-volatile memory devices;
one or more parity memory devices, wherein the one or more parity memory devices are a different type of non-volatile memory device than the plurality of memory devices of the primary storage array;
means for writing a block of data to the primary storage array;
means for determining parity data for the block of data;
means for selecting a size of parity data to determine for the block of data;
means for, when a combined size of the selected size of parity data and the block of data is larger than a size of a page of the primary storage array, writing at least a portion of the determined parity data to one or more parity memory devices; and
means for, when the combined size of the selected size of parity data and the block of data is smaller than or equal to the size of a page of the primary storage array, writing at least a portion of the determined parity data to the primary storage array.
12. The system of claim 11 , wherein:
the means for determining the parity data comprise means for determining first parity data and second parity data for the block of data,
the means for writing the block of data to the primary storage array comprise means for writing the block of data and the first parity data to a page of the primary storage array, and
the means for writing the portion of the parity data to the one or more parity devices comprise means for writing the second parity data to the one or more parity devices.
13. The non-transitory storage device of claim 1 , wherein the plurality of non-volatile memory devices of the primary storage array comprise a plurality of flash memory devices, and wherein the one or more parity memory devices comprise one or more magnetoresisitve random-access memory (MRAM) memory devices.
14. The non-transitory computer-readable storage medium of claim 9 , wherein the plurality of non-volatile memory devices of the primary storage array comprise a plurality of flash memory devices, and wherein the one or more parity memory devices comprise one or more magnetoresisitve random-access memory (MRAM), or phase-change random-access memory (PRAM) memory devices.
15. The system of claim 11 , wherein the plurality of non-volatile memory devices of the primary storage array comprise a plurality of flash memory devices, and wherein the one or more parity memory devices comprise one or more phase-change random-access memory (PRAM) memory devices.