IP Library Patent Application 18493379
Patent Application
App. No. 18/493,379

MICRO SOLDER JOINT AND STENCIL APERTURE DESIGN

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Quick Facts
Patent No.
US None
App. No.
18/493,379
Abstract

Micro solder joint and stencil design. In one embodiment, a stencil for depositing solder on a printed circuit board (PCB) includes a plurality of stencil apertures, a first stencil aperture of the plurality of apertures having an aperture wall defining an aperture perimeter. The aperture wall is configured to not extend beyond an outer edge of a PCB pad provided on the printed circuit board, the aperture wall is also configured to not extend beyond an outer edge of a terminal of a surface mount component, and the first stencil aperture is configured to receive solder paste to form a non-convex solder joint between the PCB pad and the terminal.

Claims (12)

1 . A stencil for depositing solder on a printed circuit board (PCB), the stencil comprising:

a plurality of stencil apertures, a first stencil aperture of the plurality of stencil apertures having an aperture wall defining an aperture perimeter,

wherein the aperture wall is configured to not extend beyond an outer edge of a PCB pad provided on the PCB,

wherein the aperture wall is configured to not extend beyond an outer edge of a terminal of a surface mount component, and

wherein the first stencil aperture is configured to receive solder paste to form a non-convex solder joint between the PCB pad and the terminal.

2 . The stencil of claim 1 , wherein the non-convex solder joint is a concave solder joint.

3 . The stencil of claim 1 , wherein the non-convex solder joint is a straight solder joint.

4 . The stencil of claim 1 , wherein a maximum principal stress level exerted by the non-convex solder joint is less than or equal to 42 megapascal (MPa).

5 . The stencil of claim 4 , wherein the non-convex solder joint is a concave solder joint, wherein the maximum principal stress level exerted by the concave solder joint is approximately equal to 30 MPa.

6 . The stencil of claim 1 , wherein a portion of the aperture perimeter defined by the aperture wall has a width of approximately 0.2 millimeters (mm).

7 . The stencil of claim 1 , wherein the surface mount component is a quad flat no-lead (QFN) package.

8 . The stencil of claim 1 , wherein the first stencil aperture is configured to receive the solder paste that contacts the PCB pad and only a surface of the terminal that faces the PCB pad.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2023
From: BURKE, JOHN PATRICK; BIN AHMAD, IBRAHYM; BIN CHE ANI, FAKHROZI; BIN MOHAMED SUNAR, MOHAMAD SOLEHIN; SING, PEIR MING; RAAVI, HARI KIRAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065326/0763 →