IP Library Granted Patent US 11,907,577
Granted Patent B2
US 11,907,577 · App. 17/543,434 · Granted Feb 20, 2024

Command queuing for data storage devices

Inventors: Tomer Spector (Kibbutz Ginegar, IL); Doron Ganon (Kfar Vradim, IL); Eran Arad (Yuvalim, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,907,577
App. No.
17/543,434
Granted
Feb 20, 2024
Kind
B2
Abstract

A plurality of commands is received from at least one application. A command of the plurality of commands is to be performed by a Data Storage Device (DSD) after one or more conditions have been satisfied by the DSD. The plurality of commands is enqueued and the command is enqueued with the one or more conditions for performing the command. It is determined whether the one or more conditions have been satisfied by the DSD, and in response to determining that the one or more conditions have been satisfied by the DSD, the command is sent to the DSD for performance of the command.

Claims (35)

1. A method, comprising:

receiving a batch of commands from at least one application, wherein the commands in the batch of commands are to be sequentially sent from a host to a Data Storage Device (DSD) for performance of the commands including a command to be performed by the DSD after one or more conditions have been satisfied by the DSD;

enqueuing the batch of commands in a queue at the host to sequentially send the commands from the host to the DSD, wherein the command is enqueued in the queue with the one or more conditions for performing the command;

determining whether the one or more conditions have been satisfied by the DSD before sending the command to the DSD; and

in response to determining that the one or more conditions have been satisfied by the DSD, sending the command in sequence from the queue to the DSD for performance of the command.

2. The method of claim 1 , wherein the batch of commands is enqueued by an execution engine of the host.

3. The method of claim 2 , wherein the execution engine is a hardware accelerator of the host.

4. The method of claim 2 , wherein the execution engine determines whether the one or more conditions have been satisfied.

5. The method of claim 1 , further comprising enqueuing at least one additional command received from the at least one application while the command and the one or more conditions remain enqueued.

6. The method of claim 1 , wherein the one or more conditions provide that a DSD queue at the DSD of pending commands to be performed by the DSD is empty.

7. The method of claim 1 , wherein the one or more conditions provide that a number of pending commands at the DSD is less than or equal to a predetermined number of pending commands.

8. The method of claim 1 , wherein an interface of the host tracks a status of the DSD to determine whether a condition of the one or more conditions is satisfied.

9. A host, comprising:

a processor configured to execute at least one application;

an interface configured to send commands to a Data Storage Device (DSD); and

means for:

receiving a batch of commands from at least one application, wherein the commands in the batch of commands are to be sequentially sent from the host to the DSD for performance of the commands including a command to be performed by the DSD after one or more conditions have been satisfied by the DSD;

enqueuing the batch of commands in a queue at the host to sequentially send the commands from the host to the DSD, wherein the command is enqueued in the queue with the one or more conditions for performing the command;

determining whether the one or more conditions have been satisfied by the DSD before sending the command to the DSD; and

in response to determining that the one or more conditions have been satisfied by the DSD, sending the command in sequence from the queue to the DSD via the interface for performance of the command.

10. The host of claim 9 , wherein the batch of commands is enqueued by an execution engine of the host.

11. The host of claim 10 , wherein the execution engine is a hardware accelerator of the host.

12. The host of claim 10 , wherein the execution engine determines whether the one or more conditions have been satisfied.

13. The host of claim 9 , wherein the one or more conditions provide that a DSD queue at the DSD of pending commands to be performed by the DSD is empty.

14. The host of claim 9 , wherein the one or more conditions provide that a number of pending commands at the DSD is less than or equal to a predetermined number of pending commands.

15. The host of claim 9 , wherein the interface tracks a status of the DSD to determine whether a condition of the one or more conditions has been satisfied.

16. A non-transitory computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are executed by a processor of a host, the computer-executable instructions cause the host to:

receive a batch of commands from at least one application executed by the host, wherein the commands in the batch of commands are to be sequentially sent from the host to a Data Storage Device (DSD) for performance of the commands including a command to be performed by the DSD after one or more conditions have been satisfied by the DSD;

enqueue the batch of commands in a queue at the host to sequentially send the commands from the host to the DSD, wherein the command is enqueued in the queue with the one or more conditions for performing the command;

determine whether the one or more conditions have been satisfied by the DSD before sending the command to the DSD; and

in response to determining that the one or more conditions have been satisfied by the DSD, send the command in sequence from the queue to the DSD for performance of the command.

17. The non-transitory computer-readable storage medium of claim 16 , wherein when the computer-executable instructions are executed by the processor of the host, the computer-executable instructions further cause the host to enqueue at least one additional command received from the at least one application while the command and the one or more conditions remain enqueued.

18. The non-transitory computer-readable storage medium of claim 16 , wherein when the computer-executable instructions are executed by the processor of the host, the computer-executable instructions further cause the host to monitor a queue status of the DSD to determine whether a condition of the one or more conditions has been satisfied.

19. The non-transitory computer-readable storage medium of claim 16 , wherein the one or more conditions provide that a DSD queue at the DSD of pending commands to be performed by the DSD is empty.

20. The non-transitory computer-readable storage medium of claim 16 , wherein the one or more conditions provide that a number of pending commands at the DSD is less than or equal to a predetermined number of pending commands.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2021
From: SPECTOR, TOMER; GANON, DORON; ARAD, ERAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058311/0812 →
Continuity (1)
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