IP Library Granted Patent US 9,792,069
Granted Patent B2
US 9,792,069 · App. 14/500,937 · Granted Oct 17, 2017

Offline deduplication for solid-state storage devices

Inventors: Gunter Knestele (Costa Mesa, CA); Jeffrey L. Furlong (Irvine, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0641G06F3/0619G06F3/0679
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Quick Facts
Patent No.
US 9,792,069
App. No.
14/500,937
Granted
Oct 17, 2017
Kind
B2
Abstract

A method for managing a flash storage system includes reading flash data units from flash memory into a buffer, wherein each of the flash data units includes host data units, and determining an identifier for each host data unit. The method includes selecting a set of unique identifiers from the determined identifiers based on a number of host data units sharing the respective unique identifier. For each unique identifier in the set of unique identifier, the method includes designating one of the host data units as a master data unit, wherein the logical address of the designated host data unit is mapped to a physical address. The logical addresses of the other host data units sharing the unique identifier are remapped to the master physical address, and the physical addresses previously mapped to the remapped logical addresses are invalidated.

Claims (73)

1. A method for managing a flash storage system, comprising:

reading a plurality of flash data units from flash memory into a buffer, wherein each of the plurality of flash data units includes one or more host data units;

determining an identifier for each of the host data units read into the buffer;

selecting a set of unique identifiers from the determined identifiers based on a number of host data units that share the respective unique identifiers, wherein the set of unique identifiers excludes determined identifiers having a number of host data units that satisfy an upper threshold count; and

for each unique identifier in the set of unique identifiers:

designating a first host data unit sharing the unique identifier as a master data unit, wherein a logical address of the first host data unit is mapped to a first physical address in the flash memory in a lookup table;

remapping, in the lookup table, respective logical addresses of one or more second host data units sharing the unique identifier from respective second physical addresses in the flash memory to the first physical address in the flash memory; and

invalidating data stored at the respective second physical addresses in the flash memory.

2. The method of claim 1 , wherein the plurality of flash data units are read from the flash memory into the buffer in response to a system maintenance operation, and

wherein the method further comprises performing the system maintenance operation after the data stored at the respective second physical address has been invalidated.

3. The method of claim 1 , wherein the method further comprises:

populating a data structure based on the determined identifiers of the host data units, wherein the data structure includes an entry for each unique identifier of the determined identifiers, and wherein each entry includes a count of host data units sharing the respective unique identifier and a logical address of each host data unit sharing the respective unique identifier,

wherein the set of unique identifiers is selected by traversing the entries of the data structure and selecting a predetermined number of unique identifiers having the largest counts of host data units less than the upper threshold count.

4. The method of claim 3 , wherein the largest counts of host data units are greater than a lower threshold count.

5. The method of claim 3 , wherein the data structure comprises a B tree, and wherein each entry comprises a respective key of the B tree.

6. The method of claim 1 , further comprising, for each unique identifier in the set of unique identifiers:

storing, in a backtrace table, respective reverse mappings of the first physical address to the logical address of the first host data unit and the respective logical addresses of the one or more second host data units.

7. The method of claim 6 , further comprising:

removing from the lookup table a mapping of a logical address of a target host data unit to be modified, the logical address of the target host data unit having been mapped to the physical address of the master data unit; and

removing from the backtrace table a reverse mapping of the physical address of the master data unit to the logical address of the target host data.

8. The method of claim 6 , further comprising:

copying data from a physical address of a target host data unit to a new physical address, wherein the target host data unit is to be modified and the target host data unit is designated as the master data unit;

designating a host data unit of the new physical address as the master data unit;

remapping, in the lookup table, respective logical addresses of the second host data units to the new physical address;

updating, in the backtrace table, reverse mappings of the physical address of the target host data unit to reverse mappings of the new physical address; and

invalidating data stored at the physical address of the target host data unit.

9. The method of claim 1 , further comprising:

for each logical address associated with a unique identifier from the set of unique identifiers, setting a dedupe flag in an entry corresponding to the logical address in the lookup table, wherein the dedupe flag indicates the logical address is mapped to a unique respective physical address.

10. The method of claim 1 , wherein the plurality of flash data units comprises respective flash data units from a plurality of flash memory devices of the flash storage system, and wherein the respective flash data units from the plurality of flash memory devices are selected in response to a system maintenance operation.

11. A flash storage system comprising:

a plurality of flash memory devices;

a memory comprising a buffer; and

a controller configured to:

read a plurality of flash data units from the plurality of flash memory devices into the buffer, wherein each of the plurality of flash data units includes one or more host data units;

determine an identifier for each of the host data units read into the buffer;

select a set of unique identifiers from the determined identifiers based on a number of host data units that share the respective unique identifiers, wherein the set of unique identifiers excludes determined identifiers having a number of host data units that satisfy an upper threshold count; and

for each unique identifier in the set of unique identifiers:

designate a first host data unit sharing the unique identifier as a master data unit, wherein a logical address of the first host data unit is mapped to a first physical address in the flash memory device in a lookup table;

remap, in the lookup table, respective logical addresses of one or more second host data units sharing the unique identifier from respective second physical addresses in the flash memory device to the first physical address in the flash memory device; and

invalidate data stored at the respective second physical addresses in the flash memory device.

12. The flash storage system of claim 11 , wherein the controller is configured to read the plurality of flash data units from the plurality of flash memory devices into the buffer in response to a system maintenance operation, and

wherein the controller is further configured to perform the system maintenance operation after the data stored at the respective second physical address has been invalidated.

13. The flash storage system of claim 11 , wherein the controller is further configured to:

populate a data structure in the memory based on the determined identifiers of the host data units, wherein the data structure includes an entry for each unique identifier of the determined identifiers, and wherein each entry includes a count of host data units sharing the respective unique identifier and a logical address of each host data unit sharing the respective unique identifier,

wherein the set of unique identifiers is selected by traversing the entries of the data structure and selecting a predetermined number of unique identifiers having the largest counts of host data units less than the upper threshold count.

14. The flash storage system of claim 13 , wherein the largest counts of host data units are greater than a lower threshold count.

15. The flash storage system of claim 13 , wherein the data structure comprises a B tree, and wherein each entry comprises a respective key of the B tree.

16. The flash storage system of claim 11 , wherein controller is further configured to, for each unique identifier in the set of unique identifiers:

store, in a backtrace table, respective reverse mappings of the first physical address to the logical address of the first host data unit and the respective logical addresses of the one or more second host data units.

17. The flash storage system of claim 16 , wherein the controller is further configured to:

remove from the lookup table a mapping of a logical address of a target host data unit to be modified, the logical address of the target host data unit having been mapped to the physical address of the master data unit; and

remove from the backtrace table a reverse mapping of the physical address of the master data unit to the logical address of the target host data.

18. The flash storage system of claim 16 , wherein the controller is further configured to:

copy data from a physical address of a target host data unit to a new physical address, wherein the target host data unit is to be modified and the target host data unit is designated as a master data unit;

designate a host data unit of the new physical address as the master data unit;

remap, in the lookup table, respective logical addresses of the second host data units to the new physical address;

update, in the backtrace table, reverse mappings of the physical address of the target host data unit to reverse mappings of the new physical address; and

invalidate data stored at the physical address of the target host data unit.

19. The flash storage system of claim 11 , wherein the controller is further configured to:

for each logical address associated with a unique identifier from the set of unique identifiers, set a dedupe flag in an entry corresponding to the logical address in the lookup table, wherein the dedupe flag indicates the logical address is not mapped to a unique respective physical address.

20. The flash storage system of claim 11 , wherein the plurality of flash data units comprises respective flash data units of the plurality of flash memory devices, and wherein the respective flash data units from the plurality of flash memory devices are selected in response to a system maintenance operation.

21. A non-transitory machine-readable medium comprising instructions stored therein, which when executed by a machine, cause the machine to perform operations comprising:

reading a plurality of flash data units from flash memory into a buffer, wherein each of the plurality of flash data units includes one or more host data units;

determining an identifier for each of the host data units read into the buffer;

selecting a set of unique identifiers from the determined identifiers based on a number of host data units that share the respective unique identifiers, wherein the set of unique identifiers excludes determined identifiers having a number of host data units that satisfy an upper threshold count; and

for each unique identifier in the set of unique identifiers:

designating a first host data unit sharing the unique identifier as a master data unit, wherein a logical address of the first host data unit is mapped to a first physical address in the flash memory in a lookup table;

remapping, in the lookup table, respective logical addresses of one or more second host data units sharing the unique identifier from respective second physical addresses in the flash memory to the first physical address in the flash memory; and

invalidating data stored at the respective second physical addresses in the flash memory.

22. The non-transitory machine-readable medium of claim 21 , wherein the instructions further cause the machine to perform operations comprising:

populating a data structure based on the determined identifiers of the host data units, wherein the data structure includes an entry for each unique identifier of the determined identifiers, and wherein each entry includes a count of host data units sharing the respective unique identifier and a logical address of each host data unit sharing the respective unique identifier,

wherein the set of unique identifiers is selected by traversing the entries of the data structure and selecting a predetermined number of unique identifiers having the largest counts of host data units less than the upper threshold count.

23. The non-transitory machine-readable medium of claim 21 , wherein the plurality of flash data units are read from the flash memory into the buffer in response to a garbage collection operation.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040829/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: KNESTELE, GUNTER; FURLONG, JEFFREY L.
To: HGST NETHERLANDS B.V.
Reel/Frame 033957/0996 →
Continuity (1)
Related Publication 20160092138A1 · Mar 31, 2016