Semiconductor device including vertical bond pads
View Patent ↗The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.
1. A semiconductor die, comprising:
first and second major surfaces;
a plurality of die bond pads formed in the first major surface;
an edge extending between the first and second major surfaces;
a plurality of edge pads exposed at the edge, the plurality of edge pads being electrically coupled to the plurality of die bond pads, and the plurality of edge pads configured to receive ball bumps and/or wire bonds; and
a plurality of vertical bond pad blocks, each vertical bond pad block comprising an edge pad of the plurality of edge pads.
2. The semiconductor die of claim 1 , wherein the plurality of edge pads extend a full height of the edge between the first and second major surfaces.
3. The semiconductor die of claim 1 , wherein a vertical bond pad block of the plurality of vertical bond pad blocks further comprises a first surface exposed at the first major surface of the semiconductor die, the first surface configured to receive a ball bump and/or wire bond.
4. The semiconductor die of claim 3 , wherein the vertical bond pad block further comprises a second surface exposed at the second major surface of the semiconductor die, the second surface configured to receive a ball bump and/or wire bond.
5. The semiconductor die of claim 1 , wherein the plurality of edge pads are exposed at the edge upon dicing the semiconductor die from a wafer.
6. The semiconductor die of claim 1 , wherein the plurality of die bond pads are formed in a chip region of the semiconductor die, and the plurality of edge pads are formed in a scribe line region of the semiconductor die.
7. The semiconductor die of claim 1 , wherein the plurality of die bond pads are electrically coupled to the plurality of edge pads by one or more metallization layers within the semiconductor die.
8. The semiconductor die of claim 1 , wherein the plurality of die bond pads are electrically coupled to the plurality of edge pads by a redistribution layer formed over the first major surface.
9. A semiconductor device, comprising:
a plurality of semiconductor dies mounted together in a die stack, each semiconductor die of the plurality of semiconductor dies comprising:
first and second major surfaces,
a plurality of die bond pads formed in the first major surface,
an edge extending between the first and second major surfaces, and
a plurality of vertical bond pad blocks electrically coupled to the plurality of die bond pads, each of the plurality of vertical bond pads blocks comprising an edge pad exposed at the edge of each semiconductor die; and
electrical connectors electrically coupling the plurality of semiconductor dies to each other.
10. The semiconductor device of claim 9 , wherein the plurality of semiconductor dies directly overlap each other.
11. The semiconductor device of claim 9 , wherein the electrical connectors comprise ball bonds and/or bond wires, and wherein the edge pads of the plurality of vertical bond pad blocks are configured to receive the ball bonds and/or bond wires.
12. The semiconductor device of claim 9 , wherein the electrical connectors comprise a bond wire coupled to the edge pad of each of the semiconductor dies in the die stack.
13. The semiconductor device of claim 9 , wherein the electrical connectors comprise a ball bond coupled to edge pads of adjacent semiconductor dies in the die stack.
14. The semiconductor device of claim 9 , wherein the plurality of vertical bond pad blocks in each of the plurality of semiconductor dies further comprises surfaces exposed on at least one of the first and second major surfaces of each of the semiconductor dies.
15. The semiconductor device of claim 14 , wherein the electrical connectors are coupled to the surfaces of the vertical bond pad blocks exposed on at least one of the first and second major surfaces of each of the semiconductor dies.
16. The semiconductor device of claim 15 , wherein the electrical connectors comprise conductive bumps on the surfaces of the vertical bond pad blocks exposed on one of the first and second major surfaces of each of the semiconductor dies.
17. The semiconductor wafer of claim 9 , further comprising a passivation layer on the first major surface of a semiconductor die of the plurality of semiconductor dies, the die bond pads and vertical bond blocks of the semiconductor die buried beneath the passivation layer.
18. A semiconductor device, comprising:
a plurality of semiconductor dies mounted together in a die stack, each semiconductor die of the plurality of semiconductor dies comprising:
first and second major surfaces,
a plurality of die bond pads formed in the first major surface,
an edge extending between the first and second major surfaces, and
edge connector means for electrically coupling the plurality of die bond pads to the edge of each of the semiconductor dies, the edge connector means extending a full height of the edge between the first and second major surfaces; and
electrical connector means for electrically coupling the plurality of semiconductor dies to each other.
19. The semiconductor device of claim 18 , wherein the plurality of semiconductor dies directly overlap each other, the electrical connector means affixed to portions of the edge connector means at the edge of the semiconductor dies.