IP Library Granted Patent US 11,126,367
Granted Patent B2
US 11,126,367 · App. 15/921,375 · Granted Sep 21, 2021

Storage system and method for determining ecosystem bottlenecks and suggesting improvements

Inventor: Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0653G06F3/0604G06F3/0683
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Quick Facts
Patent No.
US 11,126,367
App. No.
15/921,375
Granted
Sep 21, 2021
Kind
B2
Abstract

A storage system and method for determining ecosystem bottlenecks and suggesting improvements are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller comprises a plurality of hardware components, at least one of the hardware components configured to communicate with the memory; a plurality of busses connecting the hardware components; a plurality of monitors, wherein each monitor is configured to collect information on utilization of a respective one of the plurality of busses; and a processor in communication with the plurality of monitors, wherein the processor is configured to: analyze the information on utilization of the busses collected from the plurality of monitors; and provide a result of the analysis to a device external to the storage system.

Claims (32)

1. A storage system comprising:

a memory; and

a controller comprising:

a plurality of hardware components, at least one of the hardware components configured to communicate with the memory;

a plurality of busses connecting the hardware components, wherein the plurality of busses are located within the controller;

a plurality of monitors, wherein each monitor is configured to collect information on bus utilization of a respective one of the plurality of busses located within the controller; and

a processor in communication with the plurality of monitors, wherein the processor is configured to:

analyze the information on bus utilization of the plurality of busses located within the controller, wherein the information on bus utilization indicates idle time versus busy time for each of the plurality of busses;

identify bottlenecks in the controller based on the analysis; and

provide suggestions to a device external to the storage system, the suggestions comprising at least one of: increasing a command queue depth, increasing a completion queue depth, decreasing a turn-around time, and changing a command sequence.

2. The storage system of claim 1 , wherein the controller is configured to analyze the information in response to at least one of the following: a general-purpose input-output (GPIO) signal, a request from a host to write a predetermined value in a register in the storage system, a predetermined command received from the host, and a firmware request generated by the processor.

3. The storage system of claim 1 , wherein the result of the analysis is provided to a host in response to a request from the host.

4. The storage system of claim 3 , wherein the request from the host comprises a Get Log Page command.

5. The storage system of claim 1 , wherein the result of the analysis is provided to an intermediate controller between the storage system and a host.

6. The storage system of claim 1 , wherein the plurality of hardware components comprises at least one of the following: a medium access control physical (MAC PHY) module, a command fetcher, a command executer, a direct memory access (DMA) module, a flash interface module, an error correction module, a control path module, and a scheduler.

7. The storage system of claim 1 , wherein all of the plurality of monitors are identical to each other.

8. The storage system of claim 1 , wherein at least one of the monitors comprises one or more of the following: a bus parser, a power estimator, an efficiency evaluator, a performance calculator, an idle time counter, a transfer size counter, an error transaction counter, an unaligned transaction counter, an aligned transaction counter, an average outstanding commands module, a latency measurement module, a priority transaction counter, a special transaction counter, and a cache operation counter.

9. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

10. The storage system of claim 1 , wherein the information of bus utilization of the plurality of busses located in the controller comprises at least one of: peak performance of the busses, estimated peak power consumption by the busses, estimated average power consumed by the busses, total byte count transferred by the busses, latency of the busses, number of outstanding requests sent on the busses, an attribute of a transaction sent on the busses, and an error transaction on the busses.

11. The storage system of claim 10 , wherein at least one monitor of the plurality of monitors is configured to collect the bus utilization information on the fly.

12. The storage system of claim 1 , wherein the controller enables creating an adaptive ecosystem that improves itself, wherein the suggestions provided to the connected system to overcome the bottlenecks are provided on the fly.

13. A storage system comprising:

a controller comprising:

a plurality of hardware components; and

a plurality of busses connecting the hardware components, wherein the plurality of busses are located within the controller;

means for collecting information on bus utilization of the plurality of busses located within the controller,

means for analyzing the information on bus utilization of the plurality of busses located within the controller, wherein the information on bus utilization indicates idle time versus busy time for each of the plurality of busses;

means for identifying bottlenecks in a controller based on the analysis; and

means for providing suggestions to a host, wherein the suggestions comprise at least one of:

increasing a command queue depth, increasing a completion queue depth, decreasing a turn-around time, and changing a command sequence.

14. The storage system of claim 13 , wherein the storage system is removable connectable to the host.

15. The storage system of claim 13 , wherein the storage system is embedded in the host.

Assignments (8)
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2018
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045209/0834 →
Continuity (1)
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