System and method for adaptive early completion posting using controller memory buffer
Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. Responsive to receiving the interrupt, the host device access the completion queue to access entries placed by the memory device therein. The host device may take a certain amount of time to service the interrupt resulting in host latency. Given knowledge of the host latency, the memory device time the sending of the interrupt so that, given the host latency, the memory device may post the entry to the completion queue in a timely manner.
1. A method comprising:
in a memory device:
receiving a request from a host device to read a queue, the queue indicative of execution of commands by the memory device;
in response to the request, determining whether, within a predetermined time period after receiving the request, the memory device will update the queue with a status of execution of a host command; and
in response to determining that the memory device will update the queue within the predetermined time period, delaying responding to the request until after the memory device updates the queue with the status of execution of the host command.
2. The method of claim 1 , wherein the queue comprises a completion queue indicative of completion by the memory device of host commands.
3. The method of claim 2 , wherein updating the queue with the status of execution of the host command comprises updating the completion queue to indicate that execution of the host command has been completed.
4. The method of claim 3 , wherein the memory device comprises a buffer configured to store the completion queue.
5. The method of claim 1 , wherein the predetermined time period comprises a predetermined time.
6. The method of claim 1 , wherein the predetermined time period comprises a predetermined number of processing cycles.
7. A non-volatile memory device comprising:
a non-volatile memory;
a communication interface configured to communicate with a host device; and
a controller in communication with the non-volatile memory and the communication interface, the controller comprising a controller memory buffer configured to store a completion queue and configured to:
complete execution of a first command;
post a first entry to the completion queue, the first entry indicative of completion of execution of the first command;
receive a request from the host device to read the completion queue resident in the controller memory buffer, the completion queue indicative of completion of execution of commands placed by the host device on a corresponding submission queue;
in response to receiving the request, determine whether to delay responding to the request based on anticipated future activity in the completion queue, wherein the anticipated future activity comprises updating, within a predetermined time period after receiving the request, the completion queue with a second entry, the second entry indicative of completion of a second command; and
in response to determining to delay responding, delay responding to the request until after the controller performs the anticipated future activity in the completion queue.
8. The memory device of claim 7 , wherein the controller is further configured to:
send an interrupt to the host device, wherein receiving the interrupt causes the host device to access the first entry posted to the completion queue.
9. The memory device of claim 7 , wherein the controller is further configured to send an interrupt to the host device, the interrupt indicative to the host device to send the request to read the completion queue.
10. The memory device of claim 9 , wherein:
the controller memory buffer is further configured to store a sequential queue, the host device configured to cause one or more commands to be stored on the sequential queue for execution by the memory device; and
the controller is further configured to:
responsive to the host device causing the one or more commands to be stored on the sequential queue, fetch the one or more commands stored on the sequential queue;
begin execution of the one or more fetched commands; and
send the interrupt to the host device prior to completing execution of the one or more fetched commands.
11. The memory device of claim 10 , wherein the controller is configured to determine whether to delay responding to the request based on the controller determining that the one or more fetched commands have begun execution but have not completed execution.
12. A non-volatile memory device comprising:
a non-volatile memory;
means for receiving a request from a host device to read a completion queue, the completion queue indicative of completion of execution of commands, at least one of the commands for reading data from or writing data to the non-volatile memory;
means for determining, in response to the request, whether, within a predetermined time period after receiving the request, the memory device will update the completion queue with a status of execution of a host command; and
means for delaying responding to the request from the host device until after the memory device updates the completion queue with the status of execution of the host command in response to determining that the memory device will update the completion queue within the predetermined time period.
13. The non-volatile memory device of claim 12 , wherein the predetermined time period comprises a predetermined time or a predetermined number of processing cycles.
14. The non-volatile memory device of claim 12 , further comprising means for storing the completion queue.