Storage controller managing completion timing, and operating method thereof
A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.
1 . A storage controller comprising:
a command manager configured to receive a first submission queue doorbell from an external device, to fetch a first command including a first latency from the external device in response to the first submission queue doorbell, and to determine a first timing to write a first completion into the external device by adding a time period corresponding to the first latency to a time point at which the first command is fetched, the first completion indicating that the first command is completely processed; and
a direct memory access (DMA) engine configured to receive a request signal requesting processing of the first command from the command manager, to transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and to output a complete signal, which indicates that the first command is completely processed, to the command manager,
wherein the command manager writes the first completion based on the complete signal from the DMA engine and based on the first timing.
2 . The storage controller of claim 1 , wherein the command manager includes:
a latency calculator configured to calculate a time point to write the first completion into a completion queue based on the first latency; and
a timing controller configured to determine the first timing at which to write the first completion into the completion queue based on the calculated time point.
3 . The storage controller of claim 1 , wherein the command manager is configured to:
receive a second submission queue doorbell from the external device;
fetch a second command including a second latency from the external device in response to the second submission queue doorbell; and
determine a second timing to write a second completion into the external device based on the second latency, the second completion indicating that the second command is completely processed.
4 . The storage controller of claim 3 , wherein the second timing to write the second completion is prior to the first timing to write the first completion, and
the first latency includes a first interval latency indicating a time period from a time point at which the second completion is written to a time point at which the first completion is to be written.
5 . The storage controller of claim 3 , wherein the first latency includes a first processing latency indicating a time period from the time point at which the first command is fetched to a time point at which the first completion is to be written into a completion queue,
the second latency includes a second processing latency indicating a time period from a time point at which the second command is fetched to a time point at which the second completion is to be written into the completion queue, and
the command manager is configured to determine an order of processing the first command and the second command, based on the first processing latency and the second processing latency.
6 . The storage controller of claim 1 , wherein the DMA engine stores data into a nonvolatile memory device or reads data stored in the nonvolatile memory device, without a control of the external device.
7 . A storage device comprising:
a nonvolatile memory device; and
a storage controller including:
a command manager configured to receive a first submission queue doorbell from an external device, to fetch a first command including a first latency from the external device in response to the first submission queue doorbell, and to determine a first timing to write a first completion into the external device by adding a time period corresponding to the first latency to a time point at which the first command is fetched, the first completion indicating that the first command is completely processed; and
a direct memory access (DMA) engine configured to receive a request signal requesting processing of the first command from the command manager, to transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and to output a complete signal, which indicates that the first command is completely processed, to the command manager,
wherein the command manager writes the first completion based on the complete signal from the DMA engine and based on the first timing.
8 . The storage device of claim 7 , wherein the command manager includes:
a latency calculator configured to calculate a time point to write the first completion into a completion queue based on the first latency; and
a timing controller configured to determine the first timing at which to write the first completion into the completion queue based on the calculated time point.
9 . The storage device of claim 7 , wherein the command manager is configured to:
receive a second submission queue doorbell from the external device;
fetch a second command including a second latency from the external device in response to the second submission queue doorbell; and
determine a second timing to write a second completion into the external device based on the second latency, the second completion indicating that the second command is completely processed.
10 . The storage device of claim 9 , wherein the second timing to write the second completion is prior to the first timing to write the first completion, and
the first latency includes a first interval latency indicating a time period from a time point at which the second completion is written to a time point at which the first completion is to be written.
11 . The storage device of claim 9 , wherein the first latency includes a first processing latency indicating a time period from the time point at which the first command is fetched to a time point at which the first completion is to be written into a completion queue,
the second latency includes a second processing latency indicating a time period from a time point at which the second command is fetched to a time point at which the second completion is to be written into the completion queue, and
the command manager is configured to determine an order of processing the first command and the second command, based on the first processing latency and the second processing latency.
12 . The storage device of claim 7 , wherein the DMA engine stores data into the nonvolatile memory device or reads data stored in the nonvolatile memory device, without a control of the external device.
13 . The storage device of claim 7 , wherein the storage controller communicates with the external device through a non-volatile memory express (NVMe) interface.
14 . A storage system comprising:
a host device;
a nonvolatile memory device; and
a storage controller including:
a command manager configured to receive a first submission queue doorbell from the host device, to fetch a first command including a first latency from the host device in response to the first submission queue doorbell, and to determine a first timing to write a first completion into the host device by adding a time period corresponding to the first latency to a time point at which the first command is fetched, the first completion indicating that the first command is completely processed; and
a direct memory access (DMA) engine configured to receive a request signal requesting processing of the first command from the command manager, to transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and to output a complete signal, which indicates that the first command is completely processed, to the command manager,
wherein the command manager writes the first completion based on the complete signal from the DMA engine and based on the first timing.
15 . The storage system of claim 14 , wherein the command manager includes:
a latency calculator configured to calculate a time point to write the first completion into a completion queue based on the first latency; and
a timing controller configured to determine the first timing at which to write the first completion into the completion queue based on the calculated time point.
16 . The storage system of claim 14 , wherein the command manager is configured to:
receive a second submission queue doorbell from the host device;
fetch a second command including a second latency from the host device in response to the second submission queue doorbell; and
determine a second timing to write a second completion into the host device based on the second latency, the second completion indicating that the second command is completely processed.
17 . The storage system of claim 16 , wherein the second timing to write the second completion is prior to the first timing to write the first completion, and
the first latency includes a first interval latency indicating a time period from a time point at which the second completion is written to a time point at which the first completion is to be written.
18 . The storage system of claim 16 , wherein the first latency includes a first processing latency indicating a time period from the time point at which the first command is fetched to a time point at which the first completion is to be written into a completion queue,
the second latency includes a second processing latency indicating a time period from a time point at which the second command is fetched to a time point at which the second completion is to be written into the completion queue, and
the command manager is configured to determine an order of processing the first command and the second command, based on the first processing latency and the second processing latency.
19 . The storage system of claim 14 , wherein the DMA engine stores data into the nonvolatile memory device or reads data stored in the nonvolatile memory device, without a control of the host device.
20 . The storage system of claim 14 , wherein the storage controller communicates with the host device through a non-volatile memory express (NVMe) interface.