Usage of data mask in DRAM write
A method and apparatus for masking errors in a DRAM write are disclosed to perform a partial write request with an SSD controller. In embodiments, write data from a host is provided to the controller that is not aligned to the DRAM data. The controller issues a read command from the LBA of a data storage device, and a corresponding write command to write the data received from the host, prior to receipt of the read data, to perform a partial write. The read data is error corrected, and in the event an error is found in the read data, bytes containing an error are masked. The read data, including masked read data, and write data are merged to form partial write data, and written to the DRAM. In certain embodiments, the partial write data may be provided to a logic analyzer to assess the masked read data for debug analysis.
1. A data storage device, comprising:
one or more memory devices;
a logic analyzer; and
a controller coupled to the one or more memory devices and the logic analyzer, wherein the controller is configured to perform a method for masking errors in a dynamic random access memory (DRAM) write, and wherein the method comprises:
issuing a read command for read data on a DRAM;
issuing a write command to write data to the DRAM;
receiving the read data;
performing error detection on the read data and detecting an error in a byte;
merging the read data with the write data to form partial write data;
aligning the partial write data using the read data;
masking the byte of the partial write data, wherein a location of the masked byte is tracked by the logic analyzer, and wherein tracking the location increases visibility of the masked byte; and
writing the masked partial write data to the DRAM.
2. The data storage device of claim 1 , wherein the error is an uncorrectable error.
3. The data storage device of claim 2 , wherein the method further comprises providing the masked byte of the partial write data is provided to a logic analyzer.
4. The data storage device of claim 3 , wherein the method further comprises generating debug information correlated to the error based on the masked byte.
5. The data storage device of claim 4 , wherein the method further comprises replacing data comprising the byte with debug data.
6. The data storage device of claim 1 , wherein the data comprises the byte is replaced by dummy data.
7. The data storage device of claim 6 , wherein the dummy data comprises debug information.
8. A controller for a data storage device, comprising:
an input/output (I/O) to one or more memory devices; and
a processor configured to execute a method for masking errors in a dynamic random access memory (DRAM) write, wherein the method comprises:
issuing a read command for read data, that includes read alignment data;
issuing a write command;
detecting an error in read data;
masking bytes of the read data that are indicated as having an error, wherein a location of the masked bytes is tracked by a logic analyzer coupled to the controller, and wherein tracking the location increases visibility of the masked bytes;
combining the read data and write data to form partial write data; and
writing the partial write data to the one or more memory devices based on the read alignment data.
9. The controller of claim 8 , wherein the method further comprises writing debug information on the masked bytes.
10. The controller of claim 9 , further comprising an I/O to a logic analyzer, the method further comprises providing the masked bytes to the logic analyzer.
11. The controller of claim 10 , wherein the detected error is an uncorrectable error.
12. The controller of claim 11 , wherein the debug information is correlated to the detected error.
13. The controller of claim 8 , wherein the method further comprises writing one or more dummy write commands comprising debug information, and marking all bytes of the dummy write commands as being masked.
14. The controller of claim 13 , wherein the method further comprises providing the one or more dummy write commands to a logic analyzer.
15. A system for storing data, comprising:
one or more memory means;
a logic analyzer; and
a controller coupled to the one or more memory means and the logic analyzer, wherein the controller is configured to carry out a method for masking errors in a dynamic random access memory (DRAM) write, and wherein the method comprises:
executing a partial write command, wherein executing a partial write command comprises:
issuing a read data command;
issuing a write command comprising write data;
receiving read data from the one or more memory means;
receiving byte alignment data;
modifying the write data based on the byte alignment data;
detecting an error in a byte of the modified write data;
masking the byte, wherein a location of the masked byte is tracked by the logic analyzer, and wherein tracking the location increases visibility of the masked byte; and
combining the read data, write data, and masked byte.
16. The system of claim 15 , wherein the method further comprises writing debug data to the masked byte.
17. The system of claim 16 , wherein the method further comprises providing the read data and masked byte to a logic analyzer and reading the debug data at the logic analyzer.
18. The system of claim 17 , wherein the debug data is correlated to the error.
19. The system of claim 18 , wherein the error is uncorrectable.
20. The system of claim 19 , wherein the method further comprises generating an error correction code (ECC) for the byte.