Electrostatic discharge protection circuit
The disclosure relates in some aspects to electrostatic discharge (ESD) protection for an electronic circuit. In some aspects, the ESD protection includes a buffer circuit that increases the slew rate of a signal that controls a discharge circuit. In some aspects, the ESD protection includes a voltage-dependent resistance circuit that adjusts a time constant of a resistive-capacitive filter based on a voltage on a supply node.
1. An electrostatic discharge protection circuit, comprising:
a discharge circuit configured to discharge current from a first node to a second node;
a first timer circuit configured to generate a first signal for a first period of time in response to an electrostatic discharge event;
an activation circuit coupled to the first timer circuit and the discharge circuit, the activation circuit configured to activate the discharge circuit for the first period of time in response to the first signal;
a second timer circuit coupled to the first timer circuit and configured to generate a second signal for a second period of time in response to the first signal, wherein the second period of time is at least twice as long as the first period of time;
a buffer circuit coupled to the second timer circuit and configured to generate a third signal in response to the second signal, the third signal configured to activate the discharge circuit; and
a second driver circuit coupled to the first timer circuit to receive the first signal and to the buffer circuit to receive the third signal, the second driver circuit configured to prevent the third signal from activating the discharge circuit in response to the first signal.
2. The electrostatic discharge protection circuit of claim 1 , wherein:
the second timer circuit is configured to generate the second signal at a first slew rate; and
the buffer circuit is configured to generate the third signal at a second slew rate that is faster than the first slew rate.
3. The electrostatic discharge protection circuit of claim 1 , wherein the buffer circuit comprises a first inverter circuit coupled to a second inverter circuit.
4. The electrostatic discharge protection circuit of claim 1 , wherein the second timer circuit comprises a voltage-dependent resistance circuit to adjust a resistive-capacitive time constant based on a voltage on the first node.
5. The electrostatic discharge protection circuit of claim 4 , wherein the voltage-dependent resistance circuit is coupled between the first node and the second node and comprises a PMOS transistor in series with a resistor directly coupled to the first node.
6. The electrostatic discharge protection circuit of claim 5 , further comprising:
a first driver circuit coupled to the first timer circuit to receive the first signal,
wherein an output of the first driver circuit is coupled to a gate of the PMOS transistor.
7. The electrostatic discharge protection circuit of claim 6 , wherein:
the second timer circuit further comprises an NMOS transistor coupled in series with the PMOS transistor;
the output of the first driver circuit is further coupled to a gate of the NMOS transistor; and
an output node for the PMOS transistor and the NMOS transistor is configured to provide the second signal.
8. The electrostatic discharge protection circuit of claim 1 , wherein:
the activation circuit comprises a PMOS transistor comprising a first gate and a drain;
the discharge circuit comprises an NMOS transistor comprising a second gate;
the first gate is coupled to the first timer circuit to receive the first signal; and
the drain is coupled to the second gate.
9. The electrostatic discharge protection circuit of claim 8 ,
wherein an output of the second driver circuit is coupled to the second gate.
10. The electrostatic discharge protection circuit of claim 1 , wherein the second timer circuit and the buffer circuit are configured to commence the second period of time after the first period of time commences and to end the second period of time after the first period of time ends.
11. The electrostatic discharge protection circuit of claim 1 , wherein the first period of time is less than 500 nanoseconds.
12. An electrostatic discharge protection circuit, comprising:
means for discharging current from a first node to a second node;
means for generating a first signal for a first period of time in response to an electrostatic discharge event;
means for activating the means for discharging for the first period of time in response to the first signal;
means for generating a second signal for a second period of time in response to the first signal, wherein the second period of time is at least twice as long as the first period of time; and
means for buffering the second signal to generate a third signal to activate the means for discharging for the second period of time; and
second means for receiving the first signal and the third signal and preventing, in response to the first signal, the third signal from driving a second means signal configured to activate the means for discharging current.
13. The electrostatic discharge protection circuit of claim 12 , wherein:
the means for generating the second signal is configured to generate the second signal at a first slew rate; and
the means for buffering is configured to generate the third signal at a second slew rate that is faster than the first slew rate.
14. The electrostatic discharge protection circuit of claim 13 , wherein the means for generating the second signal comprises means for adjusting a resistive-capacitive time constant based on a voltage on the first node.
15. The electrostatic discharge protection circuit of claim 14 , further comprising:
first means for driving a first means signal and coupled to the means for generating the first signal and the means for generating the second signal,
wherein the first means for driving the first means signal is configured to provide a fourth signal based on the first signal to the means for generating the second signal.
16. The electrostatic discharge protection circuit of claim 15 , further comprising:
second means for driving a second means signal and coupled to the means for buffering and the means for discharging,
wherein the second means for driving the second means signal is configured to generate a fifth signal based on the third signal to activate the means for discharging.
17. The electrostatic discharge protection circuit of claim 12 , wherein:
the means for generating the second signal and the means for buffering are configured to commence the second period of time after the first period of time commences and to end the second period of time after the first period of time ends, such that the first period of time and the second period of time partially overlap.
18. The electrostatic discharge protection circuit of claim 12 , wherein the first period of time is less than 500 nanoseconds.
19. An electrostatic discharge protection method, comprising:
detecting an electrostatic discharge event;
generating a first signal for a first period of time in response to the detection of the electrostatic discharge event;
activating a discharge circuit between a first node and a second node for the first period of time in response to the first signal;
generating a second signal for a second period of time in response to the first signal, wherein the second period of time is at least twice as long as the first period of time;
buffering the second signal to generate a third signal configured to activate the discharge circuit;
preventing the third signal from activating the discharge circuit during the first period of time; and
activating, after the first period of time, the discharge circuit in response to the third signal.
20. The electrostatic discharge protection method of claim 19 , wherein:
the second signal has a first slew rate; and
the third signal has a second slew rate that is faster than the first slew rate.
21. The electrostatic discharge protection method of claim 19 , wherein the generation of the second signal comprises:
adjusting a resistive-capacitive time constant of a resistive-capacitive filter based on a voltage on the first node.
22. The electrostatic discharge protection method of claim 19 , wherein:
the first period of time commences before the second period of time commences;
the second period of time ends after the first period of time ends; and
the first period of time and the second period of time partially overlap.
23. The electrostatic discharge protection method of claim 19 , wherein the first period of time is less than 500 nanoseconds.