IP Library Granted Patent US 11,424,292
Granted Patent B2
US 11,424,292 · App. 16/907,523 · Granted Aug 23, 2022

Memory array containing capped aluminum access lines and method of making the same

Inventor: Takuya Futase (Yokkaichi, JP)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
H01L27/2463G11C5/025G11C13/0002H01L45/1233
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Quick Facts
Patent No.
US 11,424,292
App. No.
16/907,523
Granted
Aug 23, 2022
Kind
B2
Abstract

A cross-point memory device includes first conductive line structures laterally extending along a first horizontal direction, an array of memory pillar structures overlying top surfaces of the first conductive line structures, such that each of the memory pillar structures includes a respective memory element, and second conductive line structures laterally extending along a second horizontal direction and overlying top surfaces of the array of memory pillar structures. At least one of the first conductive line structures and the second conductive line structures each includes a respective aluminum-containing rail and a respective metallic cap strip in contact with a top surface of the respective aluminum-containing rail.

Claims (20)

1. A method of forming a cross-point memory device, comprising:

forming a set of first conductive line structures laterally extending along a first horizontal direction over a substrate;

forming memory-level material layers over the set of first conductive line structures;

forming a set of second conductive line structures laterally extending along a second horizontal direction over top surfaces of the array of memory pillar structures; and

patterning the memory-level material layers into an array of memory pillar structures,

wherein:

each of the memory pillar structures comprises a respective memory element and

both of the first conductive line structures and the second conductive line structures each comprise a respective aluminum-containing rail and a respective metallic cap strip in contact with a top surface of the respective aluminum-containing rail;

wherein both of the first conductive line structures and the second conductive line structures are formed by:

depositing a layer stack including, from bottom to top, an aluminum layer and a refractory metal or a refractory metal alloy metallic cap material layer; and

patterning the layer stack into the set of conductive line structures, wherein each of the conductive line structures comprises the respective aluminum-containing rail that is a patterned portion of the aluminum layer and the respective metallic cap strip that is a patterned portion of the cap material layer; and

further comprising laterally recessing sidewalls of the aluminum-containing rails by selectively etching aluminum selective to the metallic cap strips during or after a first anisotropic etch process.

2. A method of forming a cross-point memory device, comprising:

forming a set of first conductive line structures laterally extending along a first horizontal direction over a substrate;

forming memory-level material layers over the set of first conductive line structures;

forming a set of second conductive line structures laterally extending along a second horizontal direction over top surfaces of the array of memory pillar structures;

patterning the memory-level material layers into an array of memory pillar structures, wherein each of the memory pillar structures comprises a respective memory element, and at least one of the first conductive line structures and the second conductive line structures each comprise a respective aluminum-containing rail and a respective metallic cap strip in contact with a top surface of the respective aluminum-containing rail; and

forming dielectric isolation rails between each laterally neighboring pair of conductive line structures by:

depositing at least one dielectric fill material between and over the conductive line structures; and

removing portions of the at least one dielectric fill material from above a horizontal plane including top surfaces of the conductive line structures using chemical mechanical planarization, wherein remaining portions of the dielectric fill material comprise the dielectric isolation rails and wherein the metallic cap strips protect the underlying aluminum-containing rails during the chemical mechanical planarization.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2020
From: FUTASE, TAKUYA
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 052998/0680 →