IP Library Granted Patent US 10,223,216
Granted Patent B1
US 10,223,216 · App. 15/798,029 · Granted Mar 5, 2019

Non-volatile storage system that reclaims bad blocks

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Quick Facts
Patent No.
US 10,223,216
App. No.
15/798,029
Granted
Mar 5, 2019
Kind
B1
Abstract

A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.

Claims (35)

1. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells arranged as groups of non-volatile memory cells; and

one or more control circuits connected to the non-volatile memory cells and configured to determine that a particular group of non-volatile memory cells is a bad group and leave the particular group idle for a period of time such that no programming or erasing is performed for the particular group during the period of time and programming is performed for other groups of non-volatile memory cells during the period of time, the one or more control circuits are configured to determine that the particular group is no longer a bad group subsequent to the period of time and use the particular group to store host data in response to determining that the group is no longer a bad group.

2. The non-volatile storage apparatus of claim 1 , wherein:

the one or more control circuits are configured to leave the particular group idle for the period of time to allow for passive self-curing of the particular group.

3. The non-volatile storage apparatus of claim 1 , wherein:

the one or more control circuits are configured to leave the particular group idle for the period of time to allow the block to self-cure without applying additional heat.

4. The non-volatile storage apparatus of claim 1 , wherein:

the one or more control circuits are configured to leave the particular group idle for the period of time to allow for self-curing of the particular group; and

the one or more control circuits are configured to determine that the particular group has successfully completed the self-curing, the determining that the particular group is no longer a bad group is performed subsequent to determining that the particular group has successfully completed the self-curing.

5. The non-volatile storage apparatus of claim 4 , wherein:

the one or more control circuits are configured to refresh the particular group in response to determining that the particular group has successfully completed the self-curing;

the one or more control circuits are configured to verify that the particular group was successfully refreshed; and

the verifying that the particular group was successfully refreshed comprises the determining that the particular group is no longer a bad group.

6. The non-volatile storage apparatus of claim 5 , wherein:

the one or more control circuits are configured to refresh the particular group by performing an erase operation on the particular group; and

the one or more control circuits are configured to verifying that the particular group was successfully refreshed by performing an erase verification.

7. The non-volatile storage apparatus of claim 4 , wherein:

the one or more control circuits are configured to determine that the particular group has not successfully completed the self-curing and, in response thereto, provide for the particular group to remain idle for an additional period of time to allow for additional self-curing.

8. The non-volatile storage apparatus of claim 4 , wherein:

the one or more control circuits are configured to determine that the particular group has successfully completed the self-curing by performing partial re-programming of known data already stored in the particular group of non-volatile memory cells, determining a bit error rate for the known data in the particular group of non-volatile memory cells after the partial re-programming and comparing the bit error rate to a reference.

9. The non-volatile storage apparatus of claim 4 , wherein:

the one or more control circuits are configured to determine that the particular group has successfully completed the self-curing by reading data already stored in the particular group of non-volatile memory cells, performing partial re-programming of the data in the particular group of non-volatile memory cells based on the reading, determining a bit error rate for the known data in the particular group of non-volatile memory cells after the partial re-programming and comparing the bit error rate to a reference.

10. The non-volatile storage apparatus of claim 1 , wherein:

the one or more control circuits are configured to use a same standard for determining whether the particular group of non-volatile memory cells is a good group or a bad group before and after the period of time.

11. The non-volatile storage apparatus of claim 1 , wherein:

the groups of non-volatile memory cells are organized into subsets of groups; and

the one or more control circuits configured to operate over time using a repeating cycle of phases, during each phase the one or more control circuits are configured to perform multiple times more memory operations on only one of the subsets of groups as compared to other sub sets.

12. The non-volatile storage apparatus of claim 1 , wherein:

the groups of non-volatile memory cells are blocks and the particular group is a particular block;

the plurality of non-volatile memory cells comprise two dimensional flash memory cells with floating gates and tunnel dielectric regions; and

the one or more control circuits are configured to determine that the particular block of non-volatile memory cells is a bad block because the particular block of non-volatile memory cells includes charge trapped in the tunnel dielectric regions.

13. The non-volatile storage apparatus of claim 1 , wherein:

the groups of non-volatile memory cells are blocks and the particular group is a particular block; and

the plurality of non-volatile memory cells comprise a monolithic three dimensional flash memory that includes vertical NAND strings having charge trapping layers.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2017
From: DUBEYKO, VIACHESLAV ANATOLYEVICH; SONG, SEUNG-HWAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043985/0673 →
Cited By (1)
US 12,572,466