IP Library Granted Patent US 11,258,465
Granted Patent B2
US 11,258,465 · App. 16/931,305 · Granted Feb 22, 2022

Content aware decoding method and system

Inventors: Dudy David Avraham (Even Yehuda, IL); Eran Sharon (Rishon Lezion, IL); Omer Fainzilber (Herzeliya, IL); Alexander Bazarsky (Holon, IL); Stella Achtenberg (Netanya, IL)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
H03M13/3927G06F17/18H03M7/6005H03M13/3972
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,258,465
App. No.
16/931,305
Granted
Feb 22, 2022
Kind
B2
Abstract

A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Claims (41)

1. A method, comprising:

obtaining data from a memory;

estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio;

determining at least one data pattern parameter for the obtained data based on the estimating the probability of the data values, wherein the at least one data pattern parameter includes information on each bit in the obtained data; and

performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

2. The method according to claim 1 , wherein the obtained data is obtained from a sliding window sample.

3. The method according to claim 1 , wherein the probability of the data values is estimated for multiple bits simultaneously.

4. The method according to claim 1 , further comprising:

performing an iterative estimation process for the data prior to the decoding process.

5. The method of claim 1 , wherein the estimating the probability is based on the source log-likelihood ratio.

6. A method, comprising:

obtaining data from a memory;

applying the data to one or more symbol nodes of a network;

estimating a probability of data value of the obtained data based on at least one of a source log-likelihood ratio, a channel log-likelihood ratio, and a symbol probability distribution list, wherein each bit in the obtained data has an associated log-likelihood ratio and is associated with a value in each bit location, and wherein the symbol probability distribution list is based on a probability of occurrence of each symbol;

determining at least one data pattern parameter for the obtained data based on the estimating, wherein the at least one data pattern parameter includes information on each bit in the obtained data; and

performing a decoding process using the at least one data pattern parameter to determine a decoded data set.

7. The method according to claim 6 , wherein estimating the probability of data value is determined during an encoding process.

8. The method according to claim 7 , wherein the estimating the probability of data value is performed by scanning the data and counting an occurrence of each symbol in the data.

9. The method of claim 6 , wherein the probability of data value is estimated during the decoding process to determine a probability of an occurrence of each symbol.

10. The method of claim 6 , wherein the estimating the probability is based on the channel log-likelihood ratio.

11. The method of claim 6 , wherein the estimating the probability is based on the symbol probability distribution list.

12. A device, comprising:

at least one memory device; and

a controller coupled to the at least one memory device, the controller configured to provide a content-aware decoding process configured to reduce a scope of the decoding process, wherein the content-aware decoding process samples a block of data in the at least one memory device to estimate bit values in the block of data based on a loci-likelihood ratio, and wherein the log-likelihood ratio is associated with a number of ones and zeroes in each bit location, and wherein the controller is further configured with a predetermined list of patches.

13. A device, comprising:

at least one memory device; and

a controller coupled to the at least one memory device, the controller configured to provide a content-aware decoding process configured to reduce a scope of the decoding process, wherein the content-aware decoding process samples a block of data in the at least one memory device to estimate bit values in the block of data based on a log-likelihood ratio, and wherein the log-likelihood ratio is associated with a number of ones and zeroes in each bit location, and wherein the content-aware decoding process resides in firmware in the controller.

14. A device, comprising:

at least one memory device; and

a controller coupled to the at least one memory device, the controller configured to:

provide a content-aware decoding process configured to reduce a scope of the decoding process, wherein the content-aware decoding process samples a block of data in the at least one memory device to estimate bit values in the block of data based on a loci-likelihood ratio, and wherein the log-likelihood ratio is associated with a number of ones and zeroes in each bit location; and

build a dictionary of patches of a length that frequently appears in a data source.

15. An arrangement, comprising:

means for obtaining data from a memory;

means for estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio;

means for determining at least one data pattern parameter for the obtained data based on the estimating the probability of the data values, wherein the at least one data pattern parameter includes information on each bit in the obtained data; and

means for performing a decoding process using the at least one data pattern parameter to determine a decoded data set.

16. The arrangement according to claim 15 , wherein the means for obtaining data obtains data from one of a memory and a solid state drive.

17. The arrangement of claim 15 , wherein the decoding process comprises setting algorithm parameters of a length of a dictionary, a word k, and an iteration per length Max_ITER.

18. The arrangement of claim 17 , wherein the decoding process further comprises using a local neighborhood and comparison to a set of function to generate a correction term for each bit.

19. The arrangement of claim 18 , wherein the decoding process further comprises updating a data source according to previous iteration and decoding outputs.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: AVRAHAM, DUDY DAVID; SHARON, ERAN; FAINZILBER, OMER; BAZARSKY, ALEXANDER; ACHTENBERG, STELLA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053256/0881 →
Continuity (2)
Division 16137256 · Sep 20, 2018
Related Publication 20200350930A1 · Nov 5, 2020