IP Library Granted Patent US 10,872,856
Granted Patent B2
US 10,872,856 · App. 16/277,467 · Granted Dec 22, 2020

Semiconductor device including through vias in molded columns

Inventors: Yazhou Zhang (Shanghai, CN); Chin-Tien Chiu (Taichung, TW); Cong Zhang (Shanghai, CN)
Assignee: Western Digital Technologies, Inc.
H01L23/5226H01L23/5386
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,872,856
App. No.
16/277,467
Granted
Dec 22, 2020
Kind
B2
Abstract

A semiconductor device is disclosed including a stack of semiconductor die. Openings are formed in the semiconductor die as they are added to the stack, which openings are aligned at different levels of the stack. The openings are filled with an electrically insulative compound to form a molded column through all semiconductor die in the stack. After all semiconductor die are added to the stack, a via may be drilled through the molded column to electrically interconnect each semiconductor die in the stack.

Claims (37)

1. A semiconductor device, comprising:

a semiconductor die;

conductive traces on the semiconductor die;

an opening formed through the semiconductor die;

a compound within the opening; and

one or more vias, comprising an electrical conductor, formed within the compound and electrically coupled to one or more conductive trace of the conductive traces;

wherein the conductive traces are formed on a layer attached to the semiconductor die, and wherein the one or more vias are formed through the layer.

2. The semiconductor device of claim 1 , wherein the conductive traces extend into the opening formed through the semiconductor die, the one or more vias formed within the compound lying in physical contact with the conductive traces.

3. The semiconductor device of claim 1 , wherein the opening comprises a number of discrete areas, with a via being formed within each discrete area.

4. The semiconductor device of claim 1 , wherein the one or more vias comprise a plurality of vias formed in the compound.

5. The semiconductor device of claim 1 , wherein the compound is one of a thermoplastic resin and thermosetting polymer.

6. The semiconductor device of claim 1 , wherein the compound is a cured compound.

7. The semiconductor device of claim 1 , wherein the opening comprises a strip across one of the length and width of the semiconductor die.

8. The semiconductor device of claim 7 , wherein the opening is along an edge of the semiconductor die.

9. A semiconductor device, comprising:

a plurality of stacked semiconductor die;

first means on surfaces of the plurality of stacked semiconductor die for conducting electrical signals;

second means, formed through the plurality of semiconductor dies, for receiving a material;

third means for filling the second means; and

fourth means formed through the third means for conducting electrical signals from the first means;

wherein the first means are formed on a layer attached to the semiconductor die, and wherein the fourth means are formed through the layer.

10. A semiconductor device, comprising:

a plurality of stacked semiconductor die;

conductive traces on surfaces of the plurality of stacked semiconductor die;

a plurality of openings, an opening of the plurality of openings formed through each semiconductor die of the plurality of semiconductor dies, wherein the plurality of openings on the plurality of stacked semiconductor dies are aligned with each other;

a compound within the plurality of openings; and

one or more vias, comprising an electrical conductor, formed through the compound in the plurality of openings and electrically coupled to one or more conductive trace of the conductive traces;

wherein the conductive traces extend into the plurality of openings formed through the plurality of semiconductor dies, the one or more vias formed within the compound lying in physical contact with the conductive traces.

11. The semiconductor device of claim 10 , wherein the a first semiconductor die of the plurality of semiconductor dies is a controller die, and at least a second semiconductor die of the plurality of semiconductor die is a memory die.

12. The semiconductor device of claim 10 , wherein the compound in the plurality of aligned openings comprises a molded column extending through each of the plurality of semiconductor dies.

13. The semiconductor device of claim 10 , wherein the plurality of openings comprise a strip across one of the length and width of the plurality of semiconductor dies.

14. The semiconductor device of claim 10 , wherein the plurality of openings comprise a number of discrete areas, with a via being formed within each discrete area.

15. The semiconductor device of claim 10 , wherein a via of the one or more vias comprises a hole straight through the plurality of semiconductor dies.

16. The semiconductor device of claim 10 , wherein the one or more vias comprise a plurality of vias formed in the compound.

17. The semiconductor device of claim 10 , wherein the compound is one of a thermoplastic resin and thermosetting polymer.

18. The semiconductor device of claim 10 , wherein the conductive traces are formed on a plurality of layers, each attached to a surface of the plurality of semiconductor dies, and wherein the one or more vias are formed through the plurality of layers.

19. The semiconductor device of claim 18 , wherein the plurality of openings are not formed through the plurality of layers.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2019
From: ZHANG, YAZHOU; CHIU, CHIN-TIEN; ZHANG, CONG
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048599/0267 →