Granted Patent B1

US 8,782,327 · App. 12/777,771 · Granted Jul 15, 2014

Abstract

Claims (65)

1. A method of managing memory operations in non-volatile solid-state memory, the method comprising:

processing an internal command comprising a read data portion from a first physical page address and a write data portion to a second physical page address;

executing the read data portion of the internal command;

before executing the write data portion of the internal command, processing a write command from a host system for writing data to a logical address in the non-volatile solid-state memory, said processing comprising:

locating, in a mapping table, a physical page address that corresponds to the logical address, the physical page address comprising the first physical page address;

executing the write command to write data to a third physical page address;

updating the physical page address in the mapping table with the third physical address; and

updating an invalid page table with information related to the first physical page address; and

cancelling the write data portion of the internal command if an entry in the invalid page table indicates that data at the first physical page address is invalid.

2. The method of claim 1 , wherein updating the invalid page table comprises updating an entry in the invalid page table to indicate that data at the first physical page address is invalid.

3. The method of claim 1 , wherein the invalid page table is implemented as a bitmask wherein a bit is used to represent a validity of data at a page address.

4. The method of claim 1 , wherein the mapping table is implemented as an array of physical chunk addresses, wherein an index into the array is used to represent logical addresses associated with the physical chunk addresses.

5. The method of claim 1 , wherein the write command is stored in a first queue.

6. The method of claim 1 , wherein the internal command is stored in a second queue.

7. The method of claim 1 , wherein the internal command comprises a garbage collection command.

8. The method of claim 1 , wherein the internal command comprises a wear-leveling command.

9. The method of claim 1 , wherein the mapping table and the invalid page table are separate tables.

10. A storage subsystem, comprising:

a non-volatile solid-state memory array;

a controller configured to process an internal command comprising a read data portion from a first physical page address and a write data portion to a second physical page address, and a write command from a host system for writing data to a logical address in the non-volatile solid-state memory array, the controller configured to maintain:

a mapping table comprising a plurality of entries indicating correspondences between logical addresses and physical addresses in the non-volatile solid-state memory array; and

an invalid page table comprising a plurality of entries indicating validity statuses of data at physical addresses in the non-volatile solid-state memory array,

the controller further configured to:

execute the read data portion of the internal command;

before executing the write data portion of the internal command, process the write command;

locate in the mapping table a physical page address that corresponds to the logical address, the physical page address comprising the first physical page address;

execute the write command to write data to a third physical page address;

update the physical page address in the mapping table with the third physical address; and

update the invalid page table with information related to the first physical page address; and

canceling the write data portion of the internal command if an entry in the invalid page table indicates that data at the first physical page address is invalid.

11. The storage subsystem of claim 10 , wherein the controller is further configured to store the write command from the host system in a first queue.

12. The storage subsystem of claim 10 , wherein the controller is further configured to store the internal command in a second queue.

13. The storage subsystem of claim 10 , wherein the invalid page table is implemented as a bitmask wherein a bit is used to represent a validity of data at a page address.

14. The storage subsystem of claim 10 , wherein the mapping table is implemented as an array of physical chunk addresses, wherein an index into the array is used to represent logical addresses associated with the physical chunk addresses.

15. The storage subsystem of claim 10 , wherein the internal command comprises a garbage collection command.

16. The storage subsystem of claim 10 , wherein the internal command comprises a wear-leveling command.

17. A method for managing the execution of write and internal memory commands, the method comprising:

receiving an internal command and a write command;

executing a read data portion of the internal command;

determining that the internal command and the write command are directed to a common location; and

before executing a write data portion of the internal command, processing the write command, said processing comprising:

executing the write command to write data to a second location;

updating a table with information related to the common location; and

blocking the write data portion of the internal command from being performed if an entry in the table indicates that data at the common location is invalid, wherein at least said blocking is performed by a processor.

18. The method of claim 17 , further comprising storing the internal command in a first queue.

19. The method of claim 18 , further comprising storing the write command in a second queue.

20. The method of claim 18 , wherein determining that the internal command and the write command are directed to a common location comprises determining that the internal command is related to data in a first physical address that was invalidated by the write command.

21. The method of claim 18 , wherein the internal command is a garbage collection command.

22. The method of claim 17 , wherein blocking the internal command comprises cancelling the internal command from being performed.

23. A storage subsystem, comprising:

a non-volatile solid-state memory array;

a controller configured to:

receive an internal command and a write command;

execute a read data portion of the internal command;

determine that the internal command and the write command are directed to a common location; and

before executing a write data portion of the internal command, process the write command, wherein the controller is further configured to process the write command by at least:

executing the write command to write data to a second location; and

updating a table with information related to the common location; and

the controller further configured to block the write data portion of the internal command from being performed if an entry in the table indicates that data at the common location is invalid.

24. The storage subsystem of claim 23 , wherein the controller is further configured to store the internal command in a first queue.

25. The storage subsystem of claim 24 , wherein the controller is further configured to store the write command in a second queue.

26. The storage subsystem of claim 24 , wherein determining that the internal command and the write command are directed to a common location comprises determining that the internal command is related to data in a first physical address that was invalidated by the write command.

27. The storage subsystem of claim 24 , wherein the internal command comprises a garbage collection command.

28. The storage subsystem of claim 24 , wherein the internal command comprises a wear-leveling command.

29. The storage subsystem of claim 23 , wherein blocking the internal command comprises cancelling the internal command from being performed.

Assignments (12)