Run-time flash die failure detection enhancement
View Patent ↗The subject technology provides implementations, which may be included as part of firmware of the flash memory device, that will not solely rely on a flash controller interpreted status but includes additional checks to the returned flash status byte. Each flash read, write, and erase command requires a status read command to determine the state of operation. Depending on the particular command issued, each bit of the returned status has a different meaning. The flash memory device firmware can check whether an illogical or inconsistent status is present. For example, if an overall pass/fail bit indicates a “pass” but a plane pass/fail bit indicates a “fail” then there could be an erroneous detection. Also, for every operation, the firmware can read status twice when the flash memory is ready. If the second status byte fails to match the first status byte then a die may be flagged as failing.
1. A method for detecting flash memory device status comprising:
detecting a program operation for a flash memory device;
determining that a time period that satisfies a program threshold time has elapsed;
sending, after the time period that satisfies the program threshold time has elapsed, a first check status command;
receiving a first signal indicating a first status;
determining the first signal indicates a ready status;
sending a second check status command after the indicated ready status from the first signal;
receiving a second signal indicating a second status;
determining whether the first signal differs from the second signal; and
providing, in response to determining that the first signal differs from the second signal, an indication of a failure of the flash memory device.
2. The method of claim 1 , wherein the flash memory device comprises a flash memory die.
3. The method of claim 1 , wherein the first signal comprises a first plurality of bits, the second signal comprises a second plurality of bits, and determining that the first signal differs from the second signal comprises determining that the first plurality of bits is different than the second plurality of bits.
4. The method of claim 3 , wherein a portion of the first plurality of bits comprises a predetermined pattern.
5. The method of claim 4 , wherein the predetermined pattern comprises a repeating sequence of a high bit and then a low bit.
6. The method of claim 1 , wherein the program threshold time corresponds to a period of time for completing a write command.
7. The method of claim 1 , further comprising:
receiving a particular signal indicating a particular status;
determining that the particular signal indicates a busy status;
sending a third check status command;
receiving a third signal indicating a third status;
determining that the third signal indicates the ready status;
sending a fourth check status command after the indicated ready status from the third signal;
receiving a fourth signal indicating a fourth status; and
determining that the fourth signal matches the third signal.
8. The method of claim 1 , further comprising:
sending, in response to the indication of the failure of the flash memory device, a reset command for the flash memory device;
sending an initialization command for the flash memory device;
detecting an error associated with the flash memory device in response to the initialization command; and
setting the flash memory device as offline in response to the detected error.
9. A flash storage system comprising:
means for detecting a program operation for a flash memory device;
means for determining that a time period that satisfies a program threshold time has elapsed;
means for sending, after the time period that satisfies the program threshold time has elapsed, a first check status command;
means for receiving a first signal indicating a first status;
means for determining whether the first signal indicates a ready status;
means for sending a second check status command after the indicated ready status from the first signal;
means for receiving a second signal indicating a second status;
means for determining whether the first signal differs from the second signal; and
means for providing, in response to determining that the first signal differs from the second signal, an indication of a failure of the flash memory device.
10. The flash storage system of claim 9 , wherein the flash memory device comprises a flash memory die.
11. The flash storage system of claim 9 , wherein the first signal comprises a first plurality of bits, the second signal comprises a second plurality of bits, and determining that the first signal differs from the second signal comprises determining that the first plurality of bits is different than the second plurality of bits.
12. The flash storage system of claim 11 , wherein a portion of the first plurality of bits comprises a predetermined pattern, and the predetermined pattern comprises a repeating sequence of a high bit and then a low bit.
13. The flash storage system of claim 9 , further comprising:
means for sending, in response to the indication of the failure of the flash memory device, a reset command for the flash memory device; means for sending an initialization command for the flash memory device; means for detecting an error associated with the flash memory device in response to the initialization command; and means for setting the flash memory device as offline in response to the detected error.
14. The flash storage system of claim 9 , further comprising:
means for determining that a particular signal indicates a busy status;
means for sending a third check status command;
means for receiving a third signal indicating a third status;
means for determining that the third signal indicates the ready status;
means for sending a fourth check status command after the indicated ready status from the third signal;
means for receiving a fourth signal indicating a fourth status; and
means for determining that the fourth signal matches the third signal.
15. A flash storage system comprising:
a plurality of flash memory devices, each of the plurality of flash memory devices including at least one flash memory die; and
a controller configured to:
detect a program operation for a flash memory device;
determine that a time period that satisfies a program threshold time has elapsed;
send, after the time period that satisfies the program threshold time has elapsed, a first check status command;
receive a first signal indicating a first status;
determine whether the first signal indicates a ready status;
send a second check status command after the indicated ready status from the first signal;
receive a second signal indicating a second status;
determine whether the first signal differs from the second signal; and
provide, in response to determining that the first signal differs from the second signal, an indication of a failure of the flash memory device.
16. The flash storage system of claim 15 , wherein the flash memory device comprises a flash memory die.
17. The flash storage system of claim 15 , wherein the first signal comprises a first plurality of bits, the second signal comprises a second plurality of bits, and determining that the first signal differs from the second signal comprises determining that the first plurality of bits is different than the second plurality of bits.
18. The flash storage system of claim 17 , wherein a portion of the first plurality of bits comprises a predetermined pattern, and the predetermined pattern comprises a repeating sequence of a high bit and then a low bit.
19. The flash storage system of claim 15 , wherein the controller is further configured to:
send, in response to the indication of the failure of the flash memory device, a reset command for the flash memory device;
send an initialization command for the flash memory device;
detect an error associated with the flash memory device in response to the initialization command; and
set the flash memory device as offline in response to the detected error.
20. The flash storage system of claim 15 , wherein the controller is further configured to:
determine that a particular signal indicates a busy status;
send a third check status command;
receive a third signal indicating a third status;
determine that the third signal indicates the ready status;
send a fourth check status command after the indicated ready status from the third signal;
receive a fourth signal indicating a fourth status; and
determine that the fourth signal matches the third signal.