Coherent access to persistent memory region range
A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.
1. A controller, comprising:
a memory comprising computer-readable instructions for a method for driverless access of a non-volatile memory of a non-volatile memory device by a host; and
a processor configured to execute instructions and cause the controller to:
initialize a Peripheral Component Interconnect express (PCIe) memory space configured to map a portion of the non-volatile memory of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device;
send load/store commands to the PCIe memory space for driverless access;
place the load/store commands in a persistent memory region (PMR) queue of the non-volatile memory device; and
aggregate the load/store commands of the PMR queue with one or more read/write commands of a Non-Volatile Memory express (NVMe) queue.
2. The controller of claim 1 , wherein the processor is further configured to cause the controller to process the load/store commands using an NVMe read path.
3. The controller of claim 1 , wherein the processor is further configured to cause the controller to process the load/store commands at a PMR of the non-volatile memory device.
4. The controller of claim 1 , wherein at least one of the load/store commands receives a higher priority than at least one of the one or more read/write commands.
5. The controller of claim 1 , wherein each of the load/store commands has additional memory allocated to conform with NVMe command payload size.
6. The controller of claim 1 , wherein the PMR queue comprises a submission queue and a command queue.
7. The controller of claim 1 , wherein the load/store commands are placed in the PMR queue by a controller of the non-volatile memory device.
8. A data storage device, comprising:
a controller configured to execute a method of driver access and driverless access of a non-volatile memory of a non-volatile memory device by a host, the method comprising:
initializing a Peripheral Component Interconnect express (PCIe) memory space configured to map a portion of the non-volatile memory of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device;
initializing a PCIe configuration space with configuration information of the non-volatile memory device;
sending load/store commands to a persistent memory region (PMR) queue of the PCIe memory space for driverless access;
sending read/write commands to a Non-Volatile Memory express (NVMe) driver of the host for driver access utilizing the configuration information of the non-volatile memory device; and
aggregating the load/store commands and the read/write commands in an aggregated command queue for processing by the non-volatile memory device.
9. The data storage device of claim 8 , wherein the PCIe memory space is initialized by activating a base address register (BAR) corresponding to a physical region of the non-volatile memory of the non-volatile memory device.
10. The data storage device of claim 8 , wherein the NVMe driver is configured to send read/write commands to an NVMe layer of the non-volatile memory device.
11. The data storage device of claim 8 , wherein at least one of the load/store commands receives a higher priority than at least one of the read/write commands.
12. The data storage device of claim 8 , wherein each of the load/store commands has additional memory allocated to conform with a command payload size of the read/write commands.
13. The data storage device of claim 8 , wherein the load/store commands are provided to the PMR queue.
14. The data storage device of claim 8 , wherein the PMR queue comprises a submission queue and a completion queue.
15. The data storage device of claim 8 , wherein the load/store commands are placed in the PMR queue by a controller of the non-volatile memory device.
16. A system for storing data, the system comprising:
one or more non-volatile memory means; and
a controller means configured to perform a method to maintain coherency between persistent memory region (PMR) and Non-Volatile Memory express (NVMe) data transactions, the method comprising:
establishing a Peripheral Component Interconnect express (PCIe) link between a host and the non-volatile memory means;
establishing an NVMe link between the host and the non-volatile memory means;
initializing a PCIe memory space configured to map one or more portions of the non-volatile memory of the non-volatile memory means to a host memory space through the PCIe link between the host and the non-volatile memory means;
sending load/store commands to the PCIe memory space for driverless access;
placing the load/store commands in a PMR queue of the non-volatile memory means; and
aggregating the load/store commands of the PMR queue with one or more read/write commands of an NVMe queue.
17. The system of claim 16 , wherein the method further comprises assigning at least one of the load/store commands a higher priority than at least one of the one or more read/write commands.
18. The system of claim 16 , wherein the method further comprises processing the load/store commands at a PMR of the non-volatile memory means.
19. The system of claim 16 , wherein the method further comprises processing the load/store commands using an NVMe read path.
20. The system of claim 16 , wherein each of the load/store commands has additional memory allocated to conform with NVMe read/write command payload size.