Asymmetric log-likelihood ratio for MLC flash channel
View Patent ↗Disclosed is an system and method for reading a flash memory cell with an adjusted read level. A current read level is adjusted to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1.
1. A computer-implemented method of reading a flash memory with an adjusted read level, the method comprising:
identifying a current read level associated with determining a most significant bit in a plurality of multi-level memory cells;
setting the current read level to a new read level associated with increasing a first error rate, the first error rate associated with determining that the most significant bit is a first binary value, to decrease a second error rate associated with determining that the most significant bit is a second binary value;
reading a memory cell with the new read level to determine a most significant bit value of the memory cell;
determining a probability value associated with the most significant bit value; and
providing the most significant bit value and the probability value to a decoder.
2. The computer-implemented method of claim 1 , wherein the probability value is representative of a likelihood that the most significant bit value is equal to a programmed level of the memory cell, and wherein the probability value is representative of a higher probability if the most significant bit value is equal to the second binary value than if the most significant bit value is equal to the first binary value.
3. The computer-implemented method of claim 1 , wherein the first binary value is a binary one and the second binary value is a binary zero.
4. The computer-implemented method of claim 1 , wherein each of the plurality of memory cells is programmed to one of four programming levels, a first and fourth programming levels being associated with the first binary value and a second and third programming levels being associated with the second binary value, and wherein the current read level is a voltage level sufficient to read a majority of memory cells programmed to the fourth programming level.
5. The computer-implemented method of claim 1 , wherein the probability value is a log-likelihood ratio.
6. The computer-implemented method of claim 1 , wherein the current read level is adjusted to the new read level after a predetermined number of program/erase cycles associated with the memory cell.
7. The computer-implemented method of claim 1 , wherein the current read level is adjusted an amount based on a cycle time associated with the memory cell.
8. The computer-implemented method of claim 1 , wherein the current read level is adjusted to the new read level after a predetermined retention time associated with the memory cell.
9. The computer-implemented method of claim 1 , wherein the current read level is adjusted an amount based on a retention time associated with the memory cell.
10. The computer-implemented method of claim 1 , wherein the new read level is representative of a lower voltage level than the current read level.
11. The computer-implemented method of claim 1 , wherein determining the probability value includes retrieving the probability value from a lookup table.
12. The computer-implemented method of claim 1 , wherein setting the current read level to a new read level includes:
retrieving an adjustment to the current read level from a lookup table; and
adjusting the current read level according to the adjustment.
13. A machine-readable medium having instructions that, when executed, perform a method of reading a flash memory with an adjusted read level, the method comprising:
identifying a current read level associated with determining between cell distributions in a plurality of multi-level memory cells;
setting the current read level to a new read level associated with increasing a chance of error of determining cells in a first cell distribution, to decrease a chance of error of determining cells in a second cell distribution;
performing a page operation to determine a group of cells at the first or second distribution;
determining probability values corresponding to the group of cells; and
providing the group of cells and the probability values to a decoder.
14. The machine-readable medium of claim 13 , wherein the first cell distribution is representative of cells having a most significant bit value of a binary one, and wherein the second cell distribution is representative of cells having a most significant bit value of a binary zero.
15. The machine-readable medium of claim 13 , wherein the probability values are representative of a likelihood that a current level of a memory cell is equal to a programmed level of the memory cell, and wherein the probability values are representative of a higher probability if corresponding memory cells are read to be in the second distribution than if the corresponding memory cells are read to be in the first distribution.
16. The machine-readable medium of claim 13 , wherein determining between cell distributions in a plurality of multi-level memory cells includes determining between logical bit values of a most significant bit.
17. The machine-readable medium of claim 13 , wherein the chance of error of determining cells in the first cell distribution and the chance of error of determining cells in the second cell distribution are realized at the decoder.
18. The machine-readable medium of claim 13 , wherein determining the probability values includes retrieving the probability values from a lookup table.
19. The machine-readable medium of claim 1 , wherein setting the current read level to a new read level includes:
retrieving an adjustment to the current read level from a lookup table; and
adjusting the current read level according to the adjustment.
20. A system, comprising:
a memory, the memory having stored thereon a plurality of programming levels and corresponding unique level distributions;
a memory interface configured to be operably coupled to the memory;
a decoder; and
a page operation unit operably coupled to the memory interface and the decoder, wherein the page operation unit is configured to:
identify the current read level associated with determining a most significant bit in a plurality of multi-level memory cells;
set the current read level to a new read level associated with increasing a first error rate, the first error rate associated with determining that the most significant bit is a first binary value, to decrease a second error rate associated with determining that the most significant bit is a second binary value;
read a memory cell with the new read level to determine a most significant bit value of the memory cell;
determine a probability value associated with the most significant bit value; and
provide the most significant bit value and the probability value to a decoder.
21. The system of claim 20 , wherein the probability value is representative of a likelihood that the most significant bit value is equal to a programmed level of the memory cell, and wherein the probability value is representative of a higher probability if the most significant bit value is equal to the second binary value than if the most significant bit value is equal to the first binary value.
22. The system of claim 20 , wherein the first binary value is a binary one and the second binary value is a binary zero.
23. The system of claim 20 , wherein each of the plurality of memory cells is programmed at one of four programming levels, a first and fourth programming levels being associated with the first binary value and a second and third programming levels being associated with the second binary value, and wherein the current read level is a voltage level sufficient to read a majority of memory cells programmed at the fourth programming level.
24. The system of claim 20 , wherein the probability value is a log domain probability.