Skip coding for fractional bit-per-cell NAND memories
View Patent ↗An apparatus and method of skip coding user data is provided. According to skip coding, for each cell in which an upper page is 0, data is stored in a half page. For each portion of data in which the upper page is 1, data is not stored in the half page. Thus, cells of a NAND memory may each store 3.5 bits, in one of twelve available states.
1. A method of encoding user data, the method comprising
encoding user data into an upper page and a half page of a plurality of portions of data; and
skip coding data in the half page such that, for each portion of data in which a bit in the upper page is 0, a bit of data is stored in the half page, and for each portion of data in which a bit in the upper page is 1, no data is stored in the half page.
2. The method of claim 1 , further comprising encoding user data into a middle page and a lower page.
3. The method of claim 1 , further comprising:
after encoding the user data into the upper page, and prior to the skip coding data in the half page;
determining if a number of is in the upper page is greater than a number of 0s in the upper page; and
if the number of is in the upper page is greater than the number of 0s in the upper page, flipping the data in the upper page such that the 1s are changed to 0s and the 0s are changed to 1s.
4. The method of claim 2 , further comprising transmitting data of the upper page, the middle page, the lower page, and the half page to a NAND memory device.
5. The method of claim 4 , further comprising:
storing the data of the upper page, the middle page, the lower page, and the half page in a plurality of cells of the NAND memory device by programming each of the plurality of cells to one of twelve available states.
6. The method of claim 1 , further comprising:
adding error correction code to the upper page and adding error correction code to the half page, wherein a volume of the error correction code added to the upper page is twice a volume of the error correction code added to the half page.
7. A method of reading data from a memory device, the method comprising:
reading an upper page of data;
error correction decoding the upper page of data;
reading a half page of data; and
skip decoding the half page of data, the skip decoding comprising, for each portion of data in which a bit in the upper page is 0, reading corresponding data from the half page, and for each portion of data in which a bit in the upper page is 1, disregarding the half page.
8. The method according to claim 7 , further comprising error correction decoding the half page of data.
9. The method according to claim 7 , further comprising:
reading a middle page of data and a lower page of data; and
error correction decoding the middle page of data and the lower page of data.
10. A memory device comprising:
a plurality of memory cells; and
a controller in communication with the memory cells, wherein the controller is configured to:
encode user data into an upper page and a half page, and
skip code data in the half page such that, for each portion of data in which a bit in the upper page is 0, a bit of data is stored in the half page, and for each portion of data in which a bit in the upper page is 1, no data is stored in the half page.
11. The memory device of claim 10 , wherein the controller is further configured to encode user data into a middle page and a lower page.
12. The memory device of claim 10 , wherein the controller is further configured to:
after encoding the user data into the upper page, and prior to the skip coding data in the half page:
determine if a number of is in the upper page is greater than a number of 0s in the upper page; and
if the number of is in the upper page is greater than the number of 0s in the upper page, flip the data in the upper page such that the 1s are changed to 0s and the 0s are changed to 1s.
13. The memory device of claim 11 , further comprising transmitting data of the upper page, the middle page, the lower page, and the half page to a NAND memory device.
14. The memory device of claim 10 , wherein the controller is further configured to:
store data of the upper page, the middle page, the lower page, and the half page in a plurality of NAND memory cells by biasing each of the plurality of cells to one of twelve available states.
15. The memory device of claim 10 , wherein the controller is further configured to:
add error correction code to the upper page and add error correction code to the half page, wherein a volume of error correction code added to the upper page is twice a volume of error correction code added to the half page.