IP Library Granted Patent US 11,137,914
Granted Patent B2
US 11,137,914 · App. 16/405,818 · Granted Oct 5, 2021

Non-volatile storage system with hybrid command

Inventors: Rotem Sela (Hod Hasharon, IL); Yiftach Tzori (Hod Hasharon, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0613G06F3/068G06F3/0655G06F3/0679G06F9/38G11C11/409
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Quick Facts
Patent No.
US 11,137,914
App. No.
16/405,818
Granted
Oct 5, 2021
Kind
B2
Abstract

A hybrid command is proposed for interacting with a non-volatile memory device. The hybrid command enables a host connected to the non-volatile memory device to both send and receive data using a single command, which removes the need to use separate commands for sending and receiving. Using the one command rather than separate commands increases system performance.

Claims (83)

1. A non-volatile memory device, comprising:

non-volatile memory; and

a processor connected to the non-volatile memory, wherein the processor is configured to:

receive a command message at the non-volatile memory device from an external entity, wherein:

the external entity is external to the non-volatile memory device,

the command message includes a command, and

the command requests an operation to be performed,

perform the operation in response to the command message, including performing a memory operation on the non-volatile memory,

receive first host data in a data transfer message from the external entity in response to the command, wherein the processor is configured to use the first host data to perform the memory operation on the non-volatile memory, and

send second host data in a data transfer message to the external entity in response to the command, wherein the processor is configured to obtain the second host data from the non-volatile memory, wherein the data transfer message from the external entity and the data transfer message to the external entity are separate messages from each other and from the command message.

2. The non-volatile memory device of claim 1 , wherein:

the processor is further configured to send a response message to the external entity, wherein the response message includes status information for the operation; and

the response message is separate from the data transfer message from the external entity, the data transfer message to the external entity, and the command message.

3. The non-volatile memory device of claim 1 , wherein:

the processor is further configured to send a message to the external entity prompting the external entity to send the first host data for the command.

4. The non-volatile memory device of claim 1 , wherein:

the command is a read command;

the first host data in the data transfer message from the external entity comprises indications of multiple physical addresses in the non-volatile memory; and

the second host data in the data transfer message to the external entity comprises data read from the non-volatile memory using one or more of the multiple physical addresses.

5. The non-volatile memory device of claim 4 , wherein:

the external entity is a host connected to the non-volatile memory device by a Universal Flash Storage (UFS) interface; and

the data transfer message from the external entity, the data transfer message to the external entity, and the command message are UFS Protocol Information Units (UPIUs).

6. The non-volatile memory device of claim 4 , wherein:

the command message includes a first transfer length indication and a second transfer length indication;

the first transfer length indication indicates the amount of data to be in the data transfer message from the external entity; and

the second transfer length indication indicates the amount data to be transmitted in the data transfer message to the external entity.

7. The non-volatile memory device of claim 1 , wherein:

the second host data comprises data to be written to the non-volatile memory.

8. The non-volatile memory device of claim 1 , wherein:

the first host data received in the data transfer message from the external entity comprises multiple physical addresses in the non-volatile memory.

9. The non-volatile memory device of claim 1 , wherein:

the first host data received in the data transfer message from the external entity comprises data to be written to the non-volatile memory.

10. The non-volatile memory device of claim 1 , wherein:

the command is a write command;

the first host data in the data transfer message from the external entity comprises data to be written to the non-volatile memory; and

the second host data in the data transfer message to the external entity comprises data to be written to the non-volatile memory.

11. The non-volatile memory device of claim 1 , wherein:

the performing the operation, the receiving the first host data in the data transfer message from the external entity, and the sending the second host data in the data transfer message to the external entity all comprise the processor performing the command.

12. The non-volatile memory device of claim 1 , wherein:

the non-volatile memory is flash memory;

the external entity is a host configured to be connected to the non-volatile memory device by a Universal Flash Storage (UFS) interface;

the processor is a controller that is in communication with the host;

the data transfer message from the external entity is received by the controller prior to the performing the operation in response to the command message; and

the controller is configured to perform the memory operation on the non-volatile memory by sending instructions to the non-volatile memory.

13. The non-volatile memory device of claim 1 , wherein:

the command is a read command;

the processor is further configured to transmit a ready to transfer message from the memory device to the host in response to the read command, the received data transfer message from the external entity is in response to the ready to transfer message;

the first host data in the data transfer message from the external entity comprises a plurality of indications of multiple physical addresses in the non-volatile memory; and

the second host data in the data transfer message to the external entity comprises data read from the non-volatile memory using one or more of the multiple physical addresses.

14. A method of operating non-volatile storage, the method comprising:

maintaining logical to physical address translation information at a host, wherein the logical to physical address translation information comprises a set of records each of which includes an indication of a logical address and an indication of a physical address;

transmitting a read command message from the host to a memory device including sending a read command from the host to the memory device;

transmitting a ready to transfer message from the memory device to the host in response to the read command;

transmitting a data transfer message from the host to the memory device in response to the ready to transfer message and the read command, wherein the data transfer message includes a plurality of indications of physical addresses in the memory device;

the memory device performing read operations for the physical addresses of the data transfer message in response to the read command;

transmitting data read during the read operations in one or more messages from the memory device to the host; and

transmitting a response message from the memory device to the host, wherein the response message includes status information for the operation.

15. The method of claim 14 , wherein:

the host is connected to the memory device by a Universal Flash Storage (UFS) interface; and

the read command message, the ready to transfer message, the data transfer message from the host, the one or more messages from the memory device, and the response message are UFS Protocol Information Units (UPIUs).

16. The method of claim 14 , wherein:

the transmitting the data transfer message from the host to the memory device includes transmitting logical to physical address translation information from the memory device to the host.

17. An apparatus, comprising:

a device interface;

a memory; and

means, connected to the device interface and the memory, for:

sending a command from a host to a memory device wherein the command requests a memory operation to be performed on non-volatile memory of the memory device,

sending first host data from the host to the memory device in response to the command, wherein the first host data pertains to the memory operation on the non-volatile memory,

receiving second host data at the host from the memory device in response to the command, wherein the second host data pertains to the memory operation on the non-volatile memory, and

receiving a response at the host from the memory device in response to the command, wherein the first host data and the second host data are transmitted separately from the command.

18. The apparatus of claim 17 , wherein:

the command is a read command;

the first host data comprises indications of multiple physical addresses in the non-volatile memory;

the second host data comprises data read from the non-volatile memory using one or more of the multiple physical addresses;

the sending the command and sending the first host data comprise sending Universal Flash Storage (UFS) Protocol Information Units (UPIUs); and

the memory is configured to store logical to physical address translation information, wherein the logical to physical address translation information comprises a set of records each of which includes an indication of a logical address and an indication of a physical address.

19. The apparatus of claim 17 , wherein:

the command includes a first transfer length indication and a second transfer length indication;

the first transfer length indication indicates an amount of data to be transmitted for the first host data; and

the second transfer length indication indicates an amount data to be transmitted for the second host data.

20. The apparatus of claim 17 , wherein:

the command is a hybrid command; and

the means for sending the hybrid command further includes means for sending a standard command from the host to the memory device, wherein the standard command requests a memory operation to be performed with host data being sent from one of either the host to the memory device or the memory device to the host but host data is not to be sent both from the host to the memory device and from the memory device to the host.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2019
From: SELA, ROTEM; TZORI, YIFTACH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049637/0952 →