IP Library Granted Patent US 12,086,018
Granted Patent B2
US 12,086,018 · App. 17/899,139 · Granted Sep 10, 2024

Data retention management after power off

Inventors: Lisha Wang (Fremont, CA); James Higgins (Chandler, AZ); Yongke Sun (Pleasanton, CA); Lanlan Gu (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F11/076G06F1/30G06F11/073G11C29/52
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Quick Facts
Patent No.
US 12,086,018
App. No.
17/899,139
Granted
Sep 10, 2024
Kind
B2
Abstract

Aspects of the disclosure are directed to a storage device including a memory and a controller. In some examples, the controller is configured to measure an error rate of one or more blocks of the memory. In some examples, the controller is further configured to estimate, based at least in part on the error rate, a time shift indicative of a duration of time for which the storage device was powered off. In some examples, the controller is further configured to set a read level for multiple blocks of the memory, wherein the read level is determined based at least in part on the time shift.

Claims (49)

1. A storage device, comprising:

a memory; and

a controller coupled to the memory and configured to:

measure an error rate of one or more blocks of the memory;

estimate, based at least in part on the error rate, a time shift indicative of a duration of time for which the storage device was powered off;

set a first read level for multiple blocks of the memory, wherein the first read level is determined based at least in part on the time shift;

perform an initial read of the one or more blocks of the memory according to the first read level;

perform a read recover flow (RRF) if the initial read fails; and

perform another read of the one or more blocks of the memory according to a second read level determined via the RRF.

2. The storage device of claim 1 , wherein the error rate is a raw bit error rate (RBER).

3. The storage device of claim 1 , wherein the error rate measurement is triggered by powering on the storage device from a powered off state.

4. The storage device of claim 1 , wherein the one or more blocks of the memory are last blocks to be programmed prior to storage device being powered off.

5. The storage device of claim 4 , wherein the controller is further configured to:

save metadata associated with the one or more blocks of the memory prior to the storage device being powered off; and

read the metadata upon powering on the storage device to determine the one or more blocks of the memory for measurement of the error rate.

6. The storage device of claim 1 , wherein the controller is further configured to recycle the one or more blocks of the memory if the other read fails.

7. A method of management of data stored in a memory of a storage device, comprising:

saving metadata associated with one or more blocks of the memory prior to the storage device being powered off, the metadata indicative of the one or more blocks of the memory being a last one or more blocks of the memory to be programmed prior to the storage device being powered off;

reading the metadata upon powering on the storage device to determine the one or more blocks of the memory for measurement of an error rate;

measuring the error rate of the one or more blocks of the memory, wherein the measuring the error rate is triggered by the powering on of the storage device;

estimating, based at least in part on the error rate, a time shift indicative of a duration of time for which the storage device was powered off; and

setting a read level for multiple blocks of the memory, wherein the read level is determined based at least in part on the time shift.

8. The method of claim 7 , wherein the error rate is a raw bit error rate (RBER).

9. The method of claim 7 , wherein the error rate is a bit error rate (BER), wherein the read level is a first read level, and wherein the method further comprises:

measuring a raw bit error rate (RBER) of the one or more blocks of the memory; and

determining a second read level based on the RBER.

10. The method of claim 9 , wherein the method further comprises performing an initial read of the one or more blocks of the memory according to the first read level.

11. A non-transitory computer-readable medium having instructions stored thereon that, when executed by a storage device controller of a storage device comprising a memory, cause the storage device controller to perform operations comprising:

saving metadata associated with one or more blocks of the memory prior to the storage device being powered off, the metadata indicative of the one or more blocks of the memory being a last one or more blocks of the memory to be programmed prior to the storage device being powered off;

reading the metadata upon powering on the storage device to determine the one or more blocks of the memory for measurement of an error rate;

measuring the error rate of the one or more blocks of the memory, wherein the measuring the error rate is triggered by the powering on of the storage device;

estimating, based at least in part on the error rate, a time shift indicative of a duration of time for which the storage device was powered off; and

setting a read level for multiple blocks of the memory, wherein the read level is determined based at least in part on the time shift.

12. The non-transitory computer-readable medium of claim 11 , wherein the error rate is a bit error rate (BER), wherein the read level is a first read level, and wherein the operations further comprise:

measuring a raw bit error rate (RBER) of the one or more blocks of the memory; and

determining a second read level based on the RBER.

13. The non-transitory computer-readable medium of claim 12 , wherein the operations further comprise performing an initial read of the one or more blocks of the memory according to the first read level.

14. The non-transitory computer-readable medium of claim 13 , wherein the operations further comprise:

setting the second read level for the multiple blocks of the memory; and

performing another read of the one or more blocks of the memory according to the second read level.

15. The non-transitory computer-readable medium of claim 14 , wherein the operations further comprise:

recycling the one or more blocks of the memory if the other read fails.

16. The non-transitory computer-readable medium of claim 11 , wherein the error rate is a raw bit error rate (RBER), and wherein the operations further comprise:

performing an initial read of the one or more blocks of the memory according to the read level.

17. The non-transitory computer-readable medium of claim 16 , wherein the operations further comprise:

performing a read recover flow (RRF) if the initial read fails; and

performing another read of the one or more blocks of the memory according to another read level determined via the RRF.

18. The non-transitory computer-readable medium of claim 17 , wherein the operations further comprise:

recycling the one or more blocks of the memory if the other read fails.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2022
From: WANG, LISHA; HIGGINS, JAMES; SUN, YONGKE; GU, LANLAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 062030/0789 →