Memory device including word line contact strips and methods of forming the same
A memory device includes a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, where a first stepped cavity located inside the first alternating stack includes a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers, a memory opening vertically extending through each layer within the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements, a first insulating spacer contacting sidewalls of the first stepped cavity, and a first electrically conductive strip including a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment.
1 . A method, comprising:
forming a first alternating stack of first insulating layers and first sacrificial material layers that are interlaced along a vertical direction;
forming a first stepped cavity in the first alternating stack, wherein the first stepped cavity comprises a first stepped bottom surface containing horizontally-extending surface segments of the first sacrificial material layers;
forming a first insulating spacer contacting vertically-extending surfaces of the first stepped cavity;
forming a first continuous electrically conductive material layer over the first insulating spacer and the first stepped bottom surface;
patterning the first continuous electrically conductive material layer into first electrically conductive strips;
forming a first retro-stepped dielectric material portion in the first stepped cavity; and
replacing the first sacrificial material layers with first electrically conductive layers, wherein each of the first electrically conductive strips contacts a surface segment of a respective one of the first electrically conductive layers.
2 . The method of claim 1 , wherein:
the first stepped bottom surface comprises a M×N array of horizontally-extending surface segments of the first sacrificial material layers;
the horizontally-extending surface segments are vertically spaced apart from each other;
M is an integer in a range from 1 to 10; and
N is an integer in a range from 2 to 2 10 ; and
the first insulating spacer comprises a M×N array of vertically-extending openings therethrough.
3 . The method of claim 2 , further comprising:
forming a memory opening vertically extending through each layer within the first alternating stack; and
forming memory opening fill structure in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel.
4 . The method of claim 1 , further comprising:
forming first insulating material strips over the first continuous electrically conductive material layer; and
performing an isotropic etch process that isotropically etches portions of the first continuous electrically conductive material layer that are not masked by the first insulating material strips, wherein remaining portions of the first continuous electrically conductive material layer comprise the first electrically conductive strips.
5 . The method of claim 4 , wherein each of the first insulating material strips comprises:
a first horizontally-extending bottom strip segment located in the first stepped cavity overlying a respective one of the first sacrificial material layers;
a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack; and
a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment.
6 . The method of claim 4 , further comprising:
depositing a first dielectric fill material over the first insulating material strips after formation of the first electrically conductive strips; and
removing portions of the first dielectric fill material from outside a volume of the first stepped cavity, wherein a remaining portion of the first dielectric fill material in the volume of the first stepped cavity comprises a first retro-stepped dielectric material portion.
7 . The method of claim 6 , wherein portions of the first electrically conductive strips that overlie the first alternating stack protrude above a horizontal plane including a top surface of the first retro-stepped dielectric material portion.
8 . The method of claim 1 , wherein each of the first electrically conductive strips comprises:
a first horizontally-extending bottom strip segment that is formed directly on a respective one of the first sacrificial material layers;
a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack; and
a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment.
9 . The method of claim 1 , further comprising:
forming a second alternating stack including second insulating layers and second sacrificial material layers that are interlaced along the vertical direction over the first alternating stack;
forming a second stepped cavity in the second alternating stack, wherein the second stepped cavity comprises a second stepped bottom surface containing horizontally-extending surface segments of the second sacrificial material layers;
forming a second insulating spacer on sidewalls of the second stepped cavity;
forming second electrically conductive strips over the second insulating spacer and the second stepped bottom surface, wherein a first subset of the second electrically conductive strips is formed on a top surface of a respective one of the first electrically conductive strips;
replacing the second sacrificial material layers with second electrically conductive layers; and
forming connection via structures in electrical contact with the second electrically conductive strips.
10 . The method of claim 9 , wherein:
each of the second electrically conductive strips comprises a second horizontally-extending bottom strip segment; a second horizontally-extending top strip segment that overlies a topmost layer within the second alternating stack; and a second vertically-extending strip segment connecting the second horizontally-extending bottom strip segment and the second horizontally-extending top strip segment;
a second subset of the second electrically conductive strips is formed on a surface segment of a respective one of the horizontally-extending surface segments of the second sacrificial material layers; and
the second horizontally-extending bottom strip segment of each of the second subset of the second electrically conductive strips contacts a surface segment of a respective one of the second electrically conductive layers.
11 . A memory device, comprising:
a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, wherein a first stepped cavity located inside the first alternating stack comprises a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers;
a memory opening vertically extending through each layer within the first alternating stack;
a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel;
a first insulating spacer contacting sidewalls of the first stepped cavity; and
a first electrically conductive strip comprising a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment;
wherein the first horizontally-extending bottom strip segment comprises:
a planar horizontal bottom surface contacting a portion of a top surface of said one of the first electrically conductive layers;
a planar horizontal top surface that is parallel to the planar top surface and has a lesser width than the planar horizontal bottom surface; and
a pair of horizontally-extending tapered surfaces having a respective concave vertical cross-sectional profile.
12 . A memory device, comprising:
a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, wherein a first stepped cavity located inside the first alternating stack comprises a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers;
a memory opening vertically extending through each layer within the first alternating stack;
a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel;
a first insulating spacer contacting sidewalls of the first stepped cavity; and
a first electrically conductive strip comprising a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment;
wherein the first vertically-extending strip segment comprises:
a first planar surface contacting an inner sidewall of the first insulating spacer;
a second planar surface that is parallel to the first planar surface segment and has a lesser width than the first planar surface; and
a pair of vertically-extending tapered surfaces having a respective concave horizontal cross-sectional profile.
13 . A memory device, comprising:
a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, wherein a first stepped cavity located inside the first alternating stack comprises a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers;
a memory opening vertically extending through each layer within the first alternating stack;
a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel;
a first insulating spacer contacting sidewalls of the first stepped cavity;
a first electrically conductive strip comprising a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment; and
a first insulating material strip contacting the first horizontally-extending bottom strip segment and the first vertically-extending strip segment and not contacting the first horizontally-extending top strip segment.
14 . The memory device of claim 13 , further comprising a first retro-stepped dielectric material portion located within the first stepped cavity and contacting concave surface segments of the first electrically conductive strip, wherein a top surface of the first retro-stepped dielectric material portion is located below a horizontal plane including a topmost surface of the first electrically conductive strip.
15 . A memory device, comprising:
a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, wherein a first stepped cavity located inside the first alternating stack comprises a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers;
a memory opening vertically extending through each layer within the first alternating stack;
a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel;
a first insulating spacer contacting sidewalls of the first stepped cavity;
a first electrically conductive strip comprising a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment;
a second alternating stack overlying the first alternating stack and including second insulating layers and second electrically conductive layers that are interlaced along the vertical direction, wherein a second stepped cavity located inside the second alternating stack comprises a second stepped bottom surface containing horizontally-extending surface segments of the second electrically conductive layers, and wherein the memory opening and the memory opening fill structure vertically extend through the second alternating stack;
a second insulating spacer contacting sidewalls of the second stepped cavity; and
a second electrically conductive strip comprising a second horizontally-extending bottom strip segment contacting a top surface of the first horizontally-extending top strip segment, a second horizontally-extending top strip segment that overlies a topmost layer within the second alternating stack, and a second vertically-extending strip segment connecting the second horizontally-extending bottom strip segment and the second horizontally-extending top strip segment.
16 . The memory device of claim 15 , further comprising a third electrically conductive strip comprising a third horizontally-extending bottom strip segment contacting a top surface of one of the second electrically conductive layers, a third horizontally-extending top strip segment that overlies the topmost layer within the second alternating stack, and a third vertically-extending strip segment connecting the third horizontally-extending bottom strip segment and the third horizontally-extending top strip segment.
17 . The memory device of claim 16 , further comprising:
a first connection via structure in electrical contact with the second horizontally-extending top strip segment of the second electrically conductive strip; and
a second connection via structure in electrical contact with the third horizontally-extending top strip segment of the third electrically conductive strip.