Granted Patent B1

US 10,355,009 · App. 16/020,637 · Granted Jul 16, 2019

Inventors: James Kai (Santa Clara, CA); Zhixin Cui (Yokkaichi, JP); Murshed Chowdhury (Fremont, CA); Johann Alsmeier (San Jose, CA); Tong Zhang (Palo Alto, CA)

Assignee: SANDISK TECHNOLOGIES LLC

H01L27/11556H01L21/76877H01L21/8221H01L21/8239H01L27/11582

Abstract

Claims (45)

1. A method of forming a three-dimensional memory device, comprising:

forming a first-tier structure including a first alternating stack of first insulating layers and first spacer material layers and a first retro-stepped dielectric material portion overlying first stepped surfaces of the first alternating stack in a staircase region over a substrate, wherein each of the first spacer material layers is formed as, or is subsequently replaced with, a respective first electrically conductive layer;

concurrently forming sacrificial first-tier memory opening fill portions in the memory array region and sacrificial first-tier staircase-region opening fill portions in the staircase region;

forming a second-tier structure including a second alternating stack of second insulating layers and second spacer material layers and a second retro-stepped dielectric material portion overlying second stepped surfaces of the second alternating stack, wherein each of the second spacer material layers is formed as, or is subsequently replaced with, a respective second electrically conductive layer;

forming sacrificial memory opening fill structures and sacrificial staircase-region opening fill structures that extend from a top surface of the second-tier structure to a bottom surface of the first-tier structure;

forming memory openings by removing the sacrificial memory opening fill structures;

forming memory stack structures in the memory openings;

forming sacrificial staircase-region openings by removing the sacrificial staircase-region opening fill structures; and

forming staircase-region contact via structures contacting a respective one of the first and second electrically conductive layers in the staircase-region openings.

2. The method of claim 1 , further comprising forming lower-level dielectric material layers embedding lower-level metal interconnect structures over the substrate,

wherein:

the first-tier structure is formed over the lower-level dielectric material layers; and

the staircase-region contact via structures are formed on a respective one of the lower-level metal interconnect structures.

3. The method of claim 2 , further comprising:

laterally expanding the staircase-region openings by isotropically etching the first and second insulating layers and the first and second retro-stepped dielectric material portions selective to the first and second spacer material layers; and

forming insulating spacers at peripheral portions of the laterally expanded staircase-region openings.

4. The method of claim 3 , further comprising:

forming temporary staircase-region opening fill structures within the insulating spacers;

removing the temporary staircase-region opening fill structures selective to the insulating spacers; and

anisotropically etching the insulating spacers, wherein remaining portions of the insulating spacers include ribbed insulating spacers including annular rib regions that contact sidewalls of the first and second insulating layers and cylindrical insulating spacers contacting the first and second retro-stepped dielectric material portions.

5. The method of claim 4 , wherein:

each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel;

each sacrificial memory opening fill structure comprises a respective sacrificial first-tier memory opening fill portion;

each sacrificial staircase-region opening fill structure comprises a respective sacrificial first-tier staircase-region opening fill portion;

the first and second spacer material layers are formed as first and second sacrificial material layers; and

the method further comprises replacing the first and second sacrificial material layers with the first and second electrically conductive layers after formation of the temporary staircase-region opening fill structures and prior to removal of the temporary staircase-region opening fill structures.

6. The method of claim 2 , further comprising:

forming sacrificial first-tier contact opening fill portions through the first-tier structure concurrently with formation of the sacrificial first-tier memory opening fill portions and the sacrificial first-tier staircase-region opening fill portions; and

replacing the sacrificial first-tier contact opening fill portions with through-memory-level contact via structures contacting a respective one of the lower-level metal interconnect structures concurrently with formation of the staircase-region contact via structures.

7. The method of claim 6 , wherein:

the sacrificial first-tier contact opening fill portions comprise a sacrificial first-tier array-region opening fill portion extending through each layer in the first alternating stack; and

the through-memory-level contact via structures comprise an array-region contact via structure extending through each layer in the first alternating stack and the second alternating stack.

8. The method of claim 7 , wherein:

the sacrificial first-tier contact opening fill portions further comprise a sacrificial first-tier peripheral-region opening fill portion extending through the first retro-stepped dielectric material portion and not contacting the first alternating stack; and

the through-memory-level contact via structures further comprise a peripheral region contact via structure extending through the first and second retro-stepped dielectric material portions.

9. The method of claim 1 , wherein the sacrificial first-tier memory opening fill portions and the sacrificial first-tier staircase-region opening fill portions are formed by:

concurrently forming first-tier memory openings in the memory array region and the first-tier staircase-region openings in the staircase region employing a first etch process; and

concurrently depositing a sacrificial first-tier fill material in the first-tier memory openings and the first-tier staircase-region openings; and

removing excess portions of the sacrificial first-tier fill material from above a topmost layer of the first-tier alternating stack, wherein remaining portions of the sacrificial first-tier fill material comprise the sacrificial first-tier memory opening fill portions and the sacrificial first-tier staircase-region opening fill portions.

10. The method of claim 9 , further comprising:

concurrently forming second-tier memory openings over the sacrificial first-tier memory opening fill portions and second-tier staircase-region openings over the sacrificial first-tier staircase-region opening fill portions through the second-tier structure; and

forming sacrificial second-tier memory opening fill portions in the second-tier memory openings and sacrificial second-tier staircase-region opening fill portions in the second-tier staircase-region openings,

wherein:

each sacrificial memory opening fill structure comprises a vertical stack of a respective sacrificial first-tier memory opening fill portion and a respective sacrificial second-tier memory opening fill portion; and

each sacrificial staircase-region opening fill structure comprises a vertical stack of a respective sacrificial first-tier staircase-region opening fill portion and a respective sacrificial second-tier staircase-region opening fill portion.

Assignments (4)

Continuity (1)

Cited By (10)

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