Semiconductor chip and semiconductor device including the same
A semiconductor chip includes a substrate, a source structure disposed on the substrate, and a support pattern disposed on the source structure. Each of the source structure and the support pattern includes polysilicon. The semiconductor chip further includes an electrode structure disposed on the support pattern, and a plurality of vertical structures extending vertically through the electrode structure. The electrode structure includes a lower electrode structure disposed on the support pattern and including a plurality of lower gate electrodes and a plurality of first insulating films, a second insulating film disposed on the lower electrode structure, and an upper electrode structure disposed on the second insulating film and including a plurality of upper gate electrodes and a plurality of third insulating films. The vertical structures contact the source structure above the source structure.
1. A semiconductor chip, comprising:
a substrate;
a source structure disposed on the substrate;
a support pattern disposed on the source structure,
wherein each of the source structure and the support pattern comprises polysilicon;
an electrode structure disposed on the support pattern; and
a plurality of vertical structures extending vertically through the electrode structure,
wherein the electrode structure comprises:
a lower electrode structure disposed on the support pattern and comprising a plurality of lower gate electrodes and a plurality of first insulating films;
a second insulating film disposed on the lower electrode structure; and
an upper electrode structure disposed on the second insulating film and comprising a plurality of upper gate electrodes and a plurality of third insulating films,
wherein the vertical structures contact an upper surface of the source structure above the source structure.
2. The semiconductor chip according to claim 1 , wherein each of the vertical structures comprises:
a vertical semiconductor pattern contacting the source structure; and
a data storage pattern interposed between the vertical semiconductor pattern and the electrode structure.
3. The semiconductor chip according to claim 2 , wherein
the vertical semiconductor pattern comprises a bottom portion and a side portion forming a cup shape opened at an upper end and closed at a lower end, and
the bottom portion contacts the source structure.
4. The semiconductor chip according to claim 2 , wherein each of the vertical structures does not extend through the source structure.
5. The semiconductor chip according to claim 1 , further comprising:
a dummy vertical structure extending vertically through the electrode structure,
wherein the dummy vertical structure is directly disposed on the support pattern.
6. The semiconductor chip according to claim 5 , wherein the dummy vertical structure does not extend through the support pattern.
7. The semiconductor chip according to claim 5 , wherein the dummy vertical structure has a greater depth than each of the vertical structures.
8. The semiconductor chip according to claim 1 , further comprising:
a plurality of common source plugs disposed at opposite sides of the electrode structure, respectively, and contacting the substrate,
wherein the common source plugs are directly disposed on the support pattern in a predetermined region.
9. The semiconductor chip according to claim 1 , wherein an etch selectivity of the support pattern is different from an etch selectivity of the source structure.
10. The semiconductor chip according to claim 1 , wherein a height of the upper surface of the source structure is greater than a height of an upper surface of the support pattern in regions where the source structure contacts the vertical structures, respectively.
11. The semiconductor chip according to claim 10 , wherein the source structure contacts side and bottom portions of a vertical semiconductor pattern included in each of the vertical structures.
12. The semiconductor chip according to claim 10 , wherein the source structure contacts an insulating film disposed on a lowermost layer in the lower electrode structure.
13. The semiconductor chip according to claim 10 , wherein a height of the upper surface of the source structure is lower than a height of a lower surface of a gate electrode disposed on a lowermost layer in the lower electrode structure in regions where the source structure contacts the vertical structures, respectively.
14. A semiconductor chip, comprising:
a substrate comprising a cell array region in which cells storing data are disposed, and a connecting region in which a peripheral circuit that provides an electrical signal to the cell array region is disposed;
a source structure disposed on the substrate and comprising polysilicon;
a support pattern disposed on the source structure and comprising polysilicon;
an electrode structure disposed on the support pattern; and
a plurality of vertical structures extending vertically through the electrode structure and contacting the source structure,
wherein the electrode structure comprises:
a lower electrode structure disposed on the support pattern and comprising a plurality of lower gate electrodes and a plurality of first insulating films,
a second insulating film disposed on the lower electrode structure; and
an upper electrode structure disposed on the second insulating film and comprising a plurality of upper gate electrodes and a plurality of third insulating films,
wherein an upper surface of the substrate is flat in the cell array region.
15. The semiconductor chip according to claim 14 , wherein the vertical structures are disposed in the cell array region.
16. The semiconductor chip according to claim 14 , wherein the source structure contacts bottom portions of the vertical structures.
17. The semiconductor chip according to claim 14 , further comprising:
a plurality of common source plugs disposed in the cell array region and the connecting region, the common source plugs being provided at opposite sides of the electrode structure, respectively, and connected to the substrate,
wherein the common source plugs are directly disposed on the support pattern in a predetermined region.
18. The semiconductor chip according to claim 17 , wherein the source structure is oxidized to a predetermined thickness in regions where the source structure contacts the common source plugs, respectively.
19. The semiconductor chip according to claim 14 , further comprising:
a dummy vertical structure disposed in the cell array region and extending vertically through the electrode structure,
wherein the dummy vertical structure comprises a dummy data storage pattern having forming a cup shape opened at an upper end and closed at a lower end, and
wherein a portion of the dummy data storage pattern forming a bottom portion of the dummy data storage pattern contacts the support pattern.
20. A semiconductor device, comprising:
a main substrate;
a controller;
one or more semiconductor packages; and
a dynamic random access memory (DRAM),
wherein the controller, the one or more semiconductor packages, and the DRAM are mounted on the main substrate,
wherein each of the semiconductor packages comprises:
a package substrate;
a plurality of semiconductor chips disposed on the package substrate;
a connecting structure that connects the semiconductor chips to the package substrate; and
a molding layer that covers the semiconductor chips and the connecting structure on the package substrate,
wherein each of the semiconductor chips comprises:
a substrate;
a source structure disposed on the substrate and comprising polysilicon;
a support pattern disposed on the source structure and comprising polysilicon;
an electrode structure disposed on the support pattern; and
a plurality of vertical structures extending vertically through the electrode structure,
wherein the electrode structure comprises:
a lower electrode structure disposed on the support pattern and comprising a plurality of lower gate electrodes and a plurality of first insulating films;
a second insulating film disposed on the lower electrode structure; and
an upper electrode structure disposed on the second insulating film and comprising a plurality of upper gate electrodes and a plurality of third insulating films,
wherein the vertical structures contact an upper surface of the source structure above the source structure.