Three-dimensional memory device employing discrete backside openings and methods of making the same
Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. Memory opening fill structures are formed in the memory openings, and sacrificial backside opening fill structures are formed in the backside openings. Cavities are formed in volumes of the backside openings by removing the sacrificial backside opening fill structures. Remaining portions of the sacrificial material layers are replaced with material portions including electrically conductive layers. Each electrically conductive layer is formed as a continuous material layer including holes around the backside openings. Each electrically conductive layer is singulated into a plurality of electrically conductive strips by isotropically recessing the electrically conductive layers around each backside opening. Width-modulated cavities including expanded volumes of the backside openings are formed, and are filled with width-modulated insulating wall structures.
1. A three-dimensional semiconductor device comprising:
an alternating stack of insulating layers and electrically conductive strips located over a substrate;
a width-modulated insulating wall structure that laterally extends along a first horizontal direction and vertically extends through each layer in the alternating stack; and
groups of memory stack structures extending through the alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel,
wherein:
each insulating layer is a continuous perforated insulating layer that laterally extends through the width-modulated insulating wall structure, and the electrically conductive strips in each vertical level are discrete strips that are laterally separated from each other by the width-modulated insulating wall structure;
two electrically conductive strips in each laterally neighboring pair of electrically conductive strips that are located in the same vertical level are vertically spaced from the substrate by a same distance and are laterally spaced apart from each other by a laterally undulating portion of the width-modulated insulating wall structure;
the alternating stack includes respective stepped surfaces that extend from a bottommost layer to a topmost layer within a respective alternating stack; and
each of the electrically conductive strips includes a pair of laterally undulating lengthwise sidewalls that generally extend along the first horizontal direction and a straight widthwise sidewall that is located at the stepped surfaces and that extends along a second horizontal direction that is perpendicular to the first horizontal direction.
2. The three-dimensional semiconductor device of claim 1 , further comprising:
a retro-stepped dielectric material portion that contacts each straight widthwise sidewall of the electrically conductive strips, or is laterally spaced from each straight widthwise sidewall of the electrically conductive strips by a respective backside blocking dielectric layer; and
discrete insulating pillars that vertically extend through the retro-stepped dielectric material portion.
3. The three-dimensional semiconductor device of claim 2 , wherein:
the retro-stepped dielectric material portion overlies the stepped surfaces of the alternating stack;
each of the laterally undulating lengthwise sidewalls of the electrically conductive strips includes a plurality of concave vertical sidewalls that are adjoined among one another along vertical edges; and
each of the plurality of concave vertical sidewalls contacts a respective convex vertical sidewall of the width-modulated insulating wall structure.
4. A three-dimensional semiconductor device comprising:
an alternating stack of insulating layers and electrically conductive strips located over a substrate;
a width-modulated insulating wall structure that laterally extends along a first horizontal direction and vertically extends through each layer in the alternating stack; and
groups of memory stack structures extending through the alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel,
wherein each insulating layer is a continuous perforated insulating layer that laterally extends through the width-modulated insulating wall structure, and the electrically conductive strips in each vertical level are discrete strips that are laterally separated from each other by the width-modulated insulating wall structure; and
wherein the width-modulated insulating wall structure comprises:
ribbed beams laterally contacting a respective pair of electrically conductive strips and located at each level of the electrically conductive strips and continuously extending along the first horizontal direction; and
pillar structures contacting a respective pair of an overlying ribbed beam and an underlying ribbed beam and arranged along the first horizontal direction and laterally spaced apart from each other.
5. The three-dimensional semiconductor device of claim 4 , wherein:
each ribbed beam laterally contacting the respective pair of electrically conductive strips has a sidewall located with a same flat vertical plane that includes sidewalls of the respective pair of electrically conductive strips that laterally extend along the second horizontal direction; and
for each pair of an overlying ribbed beam and an underlying ribbed beam, the underlying ribbed beam has a greater lateral extent along the first horizontal direction than the overlying ribbed beam.
6. The three-dimensional semiconductor device of claim 4 , wherein:
each group of memory stack structures includes rows of memory stack structures that are arranged along the first horizontal direction with a first pitch; and
the ribbed beams have a variable width along the second horizontal direction that changes periodically with translation along the first horizontal direction, wherein a periodicity of modulation of the variable width is the same as the first pitch.
7. The three-dimensional semiconductor device of claim 4 , wherein:
each group of memory stack structures includes a two-dimensional periodic array of memory stack structures; and
each memory stack structure is laterally spaced from the width-modulated insulating wall structure.
8. The three-dimensional semiconductor device of claim 4 , wherein:
each group of memory stack structures includes a two-dimensional periodic array of memory stack structures; and
at least one row of memory stack structures of at least one group of memory stack structures contacts the width-modulated insulating wall structure.
9. The three-dimensional semiconductor device of claim 4 , wherein:
each insulating layer is perforated by backside openings that extend through the insulating layer;
the pillar structures extend through the respective backside openings;
each insulating layer continuously extends in spaces between the backside openings containing the pillar structures; and
the width-modulated insulating wall structure is a perforated structure containing perforations filled by the insulating layers.
10. The three-dimensional semiconductor device of claim 4 , further comprising:
a plurality of width-modulated insulating wall structures extending through the alternating stack; and
a source contact layer located between the substrate and the alternating stack and contacting a sidewall of each of the vertical semiconductor channels, wherein the plurality of width-modulated insulating wall structures contact a top surface of the source contact layer.
11. The three-dimensional memory device of claim 4 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; and
the electrically conductive strips comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device.
12. The three-dimensional memory device of claim 11 , wherein:
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive strips comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and one of the plurality of semiconductor channels including the vertical semiconductor channel, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.