Three-dimensional semiconductor memory devices
Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.
1. A three-dimensional (3D) semiconductor memory device comprising:
a substrate;
an electrode structure on a first region of the substrate, the electrode structure comprising gate electrodes stacked in a first direction that is perpendicular to a top surface of the substrate;
a first source conductive pattern between the first region of the substrate and the electrode structure;
a lower sacrificial pattern on a second region of the substrate;
an insulating layer between the second region of the substrate and the lower sacrificial pattern;
a buffer insulating layer on the lower sacrificial pattern;
a vertical semiconductor pattern that penetrates the electrode structure and the first source conductive pattern on the first region of the substrate; and
a dummy vertical pattern that penetrates the buffer insulating layer, the lower sacrificial pattern, and the insulating layer on the second region of the substrate,
wherein each of the buffer insulating layer and the insulating layer includes an oxide layer.
2. The 3D semiconductor memory device of claim 1 , wherein the lower sacrificial pattern includes a different material from that of each of the buffer insulating layer and the insulating layer.
3. The 3D semiconductor memory device of claim 2 , wherein each of the buffer insulating layer and the insulating layer includes a silicon oxide layer, and wherein the lower sacrificial pattern includes silicon.
4. The 3D semiconductor memory device of claim 1 , wherein the first source conductive pattern is in contact with sidewalls of the lower sacrificial pattern, the insulating layer, and the buffer insulating layer.
5. The 3D semiconductor memory device of claim 1 , further comprising:
a second source conductive pattern between the first source conductive pattern and the electrode structure,
wherein the first source conductive pattern and the second source conductive pattern include a semiconductor material,
wherein a concentration of dopants in the first source conductive pattern is greater than a concentration of dopants in the second source conductive pattern, and
wherein the vertical semiconductor pattern penetrates the second source conductive pattern.
6. The 3D semiconductor memory device of claim 5 , wherein the first source conductive pattern is in contact with a sidewall of the vertical semiconductor pattern.
7. The 3D semiconductor memory device of claim 5 , wherein the second source conductive pattern extends on the buffer insulating layer.
8. The 3D semiconductor memory device of claim 5 , wherein the vertical semiconductor pattern extends into the substrate.
9. The 3D semiconductor memory device of claim 1 , wherein the dummy vertical pattern is wider than the vertical semiconductor pattern in a second direction that is parallel to the top surface of the substrate.
10. The 3D semiconductor memory device of claim 9 , wherein the dummy vertical pattern extends into the substrate.
11. A three-dimensional (3D) semiconductor memory device comprising:
a substrate;
an electrode structure on a first region of the substrate, the electrode structure comprising gate electrodes that are stacked in a first direction that is perpendicular to a top surface of the substrate;
a first source conductive pattern between the first region of the substrate and the electrode structure;
a lower sacrificial pattern on a second region of the substrate;
an insulating layer between the second region of the substrate and the lower sacrificial pattern;
a buffer insulating layer on the lower sacrificial pattern;
a vertical semiconductor pattern that penetrates the electrode structure and the first source conductive pattern and extends into the first region of the substrate; and
a dummy vertical pattern that penetrates the buffer insulating layer, the lower sacrificial pattern and the insulating layer and extends into the second region of the substrate,
wherein the lower sacrificial pattern includes a different material from that of each of the buffer insulating layer and the insulating layer.
12. The 3D semiconductor memory device of claim 11 , wherein the lower sacrificial pattern includes silicon.
13. The 3D semiconductor memory device of claim 11 , wherein the first source conductive pattern includes a semiconductor material that is doped with dopants.
14. The 3D semiconductor memory device of claim 13 , wherein the first source conductive pattern includes poly-silicon that is doped with N-type dopants.
15. The 3D semiconductor memory device of claim 11 , wherein the first source conductive pattern is in contact with a sidewall of the vertical semiconductor pattern.
16. The 3D semiconductor memory device of claim 11 , wherein each of the buffer insulating layer and the insulating layer includes a silicon oxide layer.
17. The 3D semiconductor memory device of claim 11 , further comprising:
a second source conductive pattern between the first source conductive pattern and the electrode structure,
wherein the vertical semiconductor pattern penetrates the second source conductive pattern.
18. The 3D semiconductor memory device of claim 17 , wherein the second source conductive pattern extends on the buffer insulating layer.
19. The 3D semiconductor memory device of claim 17 , wherein the first source conductive pattern and the second source conductive pattern include a semiconductor material.
20. The 3D semiconductor memory device of claim 11 , wherein the first source conductive pattern is in contact with sidewalls of the lower sacrificial pattern, the insulating layer, and the buffer insulating layer.