Semiconductor device
A semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. The source layer may include at least one groove in an upper surface thereof. The stack structure may be formed over the source layer. The channel layer may pass through the stack structure. The channel layer may be in contact with the source layer. The slit may pass through the stack structure. The slit may expose the groove of the source layer therethrough. The source pick-up line may be formed in the slit and the groove. The source pick-up line may be contacted with the source layer.
1. A semiconductor device comprising:
a source layer including at least one groove in an upper surface thereof;
a conductive pattern formed in the groove;
a stack structure formed over the source layer and the conductive pattern, wherein the stack structure includes at least one lower select line, word lines and at least one upper select line;
a channel layer passing through the stack structure, the channel layer being in contact with the source layer;
a slit passing through the stack structure, the slit exposing the conductive pattern; and
a source pick-up line formed in the slit, wherein the source pick-up line passes though the conductive pattern to contact the source layer.
2. The semiconductor device of claim 1 , wherein the source pick-up line contains a metal.
3. The semiconductor device of claim 1 , further comprising an insulating spacer formed on an inner wall of the slit.
4. The semiconductor device of claim 1 , the source layer includes:
a first source layer positioned in a cell region; and
a second source layer formed on the first source layer, the second source layer including the groove.
5. The semiconductor device of claim 4 , further comprising:
a transistor positioned in a peripheral region, the transistor having a gate electrode formed of the same material as the first source layer.
6. The semiconductor device of claim 4 , further comprising:
a resistor pattern positioned in a peripheral region, the resistor pattern being positioned at the substantially same level as the second source layer.
7. The semiconductor device of claim 1 , wherein the source pick-up line has a narrower width than the conductive pattern.
8. The semiconductor device of claim 1 , wherein the slit has a narrower width than the groove.
9. The semiconductor device of claim 1 , wherein the conductive pattern contains a metal.
10. The semiconductor device of claim 1 , wherein an upper surface of the conductive pattern and the upper surface of the source layer are coplanar.
11. The semiconductor device of claim 1 , further comprising:
an oxide layer interposed between the conductive pattern and the source layer.
12. A semiconductor device comprising:
a source layer including at least one groove in an upper surface thereof;
a conductive pattern formed in the groove;
a substrate under the source layer;
a stack structure formed over the source layer and the conductive pattern, wherein the stack structure includes at least one lower select line, word lines and at least one upper select line;
a source pick-up line passing through the stack structure and the conductive pattern to contact the source layer;
a transistor having a gate electrode being positioned at the substantially same level as the source layer; and
an insulating layer interposed between the substrate and the source layer and between the substrate and the gate electrode.
13. The semiconductor device of claim 12 , wherein the source pick-up line has a narrower width than the conductive pattern.
14. The semiconductor device of claim 12 , further comprising:
a channel layer passing through the stack structure, the channel layer being in contact with the source layer.
15. A semiconductor device comprising:
a source layer positioned in a cell region, the source layer including a first source layer and a second source layer formed on the first source layer, wherein the second source layer includes at least one groove in an upper surface thereof;
a conductive pattern formed in the groove;
a stack structure formed over the source layer and the conductive pattern, wherein the stack structure includes at least one lower select line, word lines and at least one upper select line;
a source pick-up line passing through the stack structure and the conductive pattern to contact the second source layer;
a transistor positioned in a peripheral region, the transistor having a gate electrode being positioned at the substantially same level as the first source layer; and
a resistor pattern positioned in the peripheral region, the resistor pattern being positioned at the substantially same level as the second source layer.
16. The semiconductor device of claim 15 , wherein the gate electrode is formed of the same material as the first source layer.
17. The semiconductor device of claim 15 , further comprising:
a substrate under the first source layer and including the cell region and the peripheral region;
an insulating layer interposed between the substrate and the first source layer in the cell region and between the substrate and the gate electrode in the peripheral region.
18. The semiconductor device of claim 15 , wherein the resistor pattern is located over the transistor.
19. The semiconductor device of claim 15 , further comprising:
a channel layer passing through the stack structure, the channel layer being in contact with the second source layer.