Three-dimensional semiconductor device

1. A three-dimensional semiconductor device, comprising:

a lower structure;

a stacked structure on the lower structure;

a horizontal structure between the lower structure and the stacked structure; and

a vertical structure passing through the stacked structure and the horizontal structure,

wherein the stacked structure includes:

a lower group including lower gate electrodes stacked and spaced apart from each other in a vertical direction, the vertical direction being a direction perpendicular to an upper surface of the lower structure, and

an upper group including upper gate electrodes stacked and spaced apart from each other in the vertical direction,

wherein the lower group and the upper group are stacked in the vertical direction;

wherein the vertical structure includes an insulating pattern, one or more voids in the insulating pattern, a semiconductor layer on at least an outer side surface of the insulating pattern, and a dielectric structure on an outer side surface of the semiconductor layer,

wherein the dielectric structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer,

wherein the horizontal structure includes a horizontal lower pattern and a horizontal upper pattern on the horizontal lower pattern, and

wherein one of the horizontal upper pattern and the horizontal lower pattern divides the dielectric structure into a first portion and a second portion, and contacts the semiconductor layer.

2. The three-dimensional semiconductor device as claimed in claim 1 , wherein the vertical structure includes a lower vertical region passing through the lower group and an upper vertical region passing through the upper group,

wherein a lower region of the upper vertical region adjacent to the lower vertical region includes a first sidewall,

wherein an upper region of the lower vertical region adjacent to the upper vertical region includes a second sidewall, and

wherein the first sidewall is not aligned with the second sidewall in the vertical direction.

3. The three-dimensional semiconductor device as claimed in claim 1 , wherein the vertical structure includes a lower vertical region passing through the lower group and an upper vertical region passing through the upper group, and

wherein an upper region of the lower vertical region adjacent to the upper vertical region has a width greater than a width of a lower region of the upper vertical region adjacent to the lower vertical region.

4. The three-dimensional semiconductor device as claimed in claim 1 , wherein the one of the horizontal upper pattern and the horizontal lower pattern is formed of polysilicon.

5. The three-dimensional semiconductor device as claimed in claim 1 , wherein the one of the horizontal upper pattern and the horizontal lower pattern contacts the outer side surface of the semiconductor layer.

6. The three-dimensional semiconductor device as claimed in claim 1 , wherein the first portion of the dielectric structure is at a higher level than the second portion of the dielectric structure,

wherein the semiconductor layer is spaced apart from the lower structure, and

wherein the second portion of the dielectric structure includes a portion between the semiconductor layer and the lower structure.

7. The three-dimensional semiconductor device as claimed in claim 1 , wherein the vertical structure further includes a pad pattern on the insulating pattern and in contact with the semiconductor layer.

8. The three-dimensional semiconductor device as claimed in claim 7 , wherein the pad pattern includes polysilicon.

9. The three-dimensional semiconductor device as claimed in claim 1 , wherein the lower structure includes a semiconductor substrate, a peripheral circuit structure on the semiconductor substrate, and a base on the peripheral circuit structure, and

wherein the base includes a polysilicon layer.

10. The three-dimensional semiconductor device as claimed in claim 1 , further comprising a separation structure passing through the stacked structure and the horizontal structure,

wherein at least one of the horizontal upper pattern or the horizontal lower pattern includes a side surface contacting a side surface of the separation structure.

11. The three-dimensional semiconductor device as claimed in claim 10 , wherein the separation structure has a line shape in a plan view.

12. A three-dimensional semiconductor device, comprising:

a lower structure;

a stacked structure on the lower structure;

a horizontal structure between the lower structure and the stacked structure; and

a vertical structure passing through the stacked structure and the horizontal structure, wherein the stacked structure includes:

a lower group including lower gate electrodes stacked and spaced apart from each other in a vertical direction, the vertical direction being a direction perpendicular to an upper surface of the lower structure, and

an upper group including upper gate electrodes stacked and spaced apart from each other in the vertical direction,

wherein the lower group and the upper group are stacked in the vertical direction;

wherein the vertical structure includes an insulating pattern, a void in the insulating pattern, a semiconductor layer on at least an outer side surface of the insulating pattern, and a dielectric structure on an outer side surface of the semiconductor layer,

wherein a sidewall of the vertical structure includes a bending portion between a lowermost gate electrode among the upper gate electrodes and an uppermost gate electrode among the lower gate electrodes,

wherein the void is at a lower level than the lowermost gate electrode among the upper gate electrodes, and

wherein the dielectric structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer.

13. The three-dimensional semiconductor device as claimed in claim 12 , wherein a distance between the lower structure and a center of the void is greater than a distance between the lowermost gate electrode among the upper gate electrodes and the center of the void.

14. The three-dimensional semiconductor device as claimed in claim 12 , wherein the horizontal structure includes a horizontal lower pattern and a horizontal upper pattern on the horizontal lower pattern, and

wherein one of the horizontal upper pattern and the horizontal lower pattern divides the dielectric structure into a first portion and a second portion, and contacts the semiconductor layer.

15. The three-dimensional semiconductor device as claimed in claim 14 , wherein the one of the horizontal upper pattern and the horizontal lower pattern is formed of polysilicon.

16. The three-dimensional semiconductor device as claimed in claim 14 , wherein the one of the horizontal upper pattern and the horizontal lower pattern contacts the outer side surface of the semiconductor layer.

17. The three-dimensional semiconductor device as claimed in claim 12 , wherein the lower structure includes a semiconductor substrate, a peripheral circuit structure on the semiconductor substrate, and a base on the peripheral circuit structure, and

wherein the base includes a polysilicon layer.

18. The three-dimensional semiconductor device as claimed in claim 12 , further comprising a separation structure passing through the stacked structure and the horizontal structure,

wherein the separation structure includes a side surface contacting a side surface of the separation structure.

19. A three-dimensional semiconductor device, comprising:

a lower structure;

a horizontal structure on the lower structure;

a stacked structure on the horizontal structure, the stacked structure including a plurality of groups stacked in a vertical direction, each of the plurality of groups including gate electrodes stacked and spaced apart from each other in the vertical direction, the vertical direction being a direction perpendicular to an upper surface of the lower structure;

a separation structure passing through the stacked structure and the horizontal structure; and

a vertical structure passing through the stacked structure and the horizontal structure,

wherein each of the groups includes gate electrodes and interlayer insulating layers, alternately and repeatedly stacked,

wherein the vertical structure includes an insulating pattern, one or more first voids in the insulating pattern, a semiconductor layer on at least an outer side surface of the insulating pattern, and a dielectric structure on an outer side surface of the semiconductor layer,

wherein the dielectric structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer, and

wherein at least a portion of the horizontal structure includes a first side surface contacting the semiconductor layer and a second side surface contacting the separation structure.

20. The three-dimensional semiconductor device as claimed in claim 19 ,

wherein the horizontal structure includes a horizontal lower pattern and a horizontal upper pattern on the horizontal lower pattern,

wherein one of the horizontal upper pattern and the horizontal lower pattern divides the dielectric structure into a first portion and a second portion, and contacts the semiconductor layer,

wherein the one of the horizontal upper pattern and the horizontal lower pattern is formed of polysilicon, and

wherein the separation structure includes a core pattern and one or more second voids in the core pattern.