IP Library Granted Patent US 7,847,334
Granted Patent B2
US 7,847,334 · App. 12/403,919 · Granted Dec 7, 2010

Non-volatile semiconductor storage device and method of manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,847,334
App. No.
12/403,919
Granted
Dec 7, 2010
Kind
B2
Abstract

A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.

Claims (34)

1. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series,

each of the memory strings comprising:

a first columnar semiconductor layer extending in a vertical direction to a substrate;

a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and

a first conductive layer formed around the charge accumulation layer via a second insulation layer,

each of the first conductive layers being formed to expand in a two-dimensional manner, and

air gaps being formed between the first conductive layers located there above and there below.

2. The non-volatile semiconductor storage device according to claim 1 , wherein

each of the air gaps has partially provided therein an insulative fluid with lower permittivity than silicon oxide, or a solid insulation layer with lower permittivity than silicon oxide.

3. The non-volatile semiconductor storage device according to claim 1 , wherein

surfaces of the first conductive layers are silicided.

4. The non-volatile semiconductor storage device according to claim 2 , wherein

surfaces of the first conductive layers are silicided.

5. The non-volatile semiconductor storage device according to claim 1 , further comprising:

a first selection transistor connected to one end of each of the memory strings,

wherein each of the first selection transistors comprises:

a second columnar semiconductor layer in contact with the bottom surface of the first columnar semiconductor layer and extending in the vertical direction; and

a second conductive layer formed around the second columnar semiconductor layer via a third insulation layer.

6. The non-volatile semiconductor storage device according to claim 5 , further comprising:

a second selection transistor connected to the other end of each of the memory strings,

wherein each of the second selection transistors comprises:

a third columnar semiconductor layer in contact with the top surface of the first columnar semiconductor layer and extending in the vertical direction; and

a third conductive layer formed around the third columnar semiconductor layer via a fourth insulation layer.

7. The non-volatile semiconductor storage device according to claim 1 , wherein

the first conductive layers and the first columnar semiconductor layers are composed of polysilicon,

the first insulation layers are composed of silicon oxide,

the second insulation layers are composed of aluminum oxide, and

the charge accumulation layers are composed of silicon nitride.

8. The non-volatile semiconductor storage device according to claim 5 , wherein

the second conductive layers and the second columnar semiconductor layers are composed of polysilicon, and

the third insulation layers are composed of silicon oxide.

9. The non-volatile semiconductor storage device according to claim 6 , wherein

the third conductive layers and the third columnar semiconductor layers are composed of polysilicon, and

the fourth insulation layers are composed of silicon oxide.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2009
From: KATSUMATA, RYOTA; KITO, MASARU; TANAKA, HIROYASU; KIDOH, MASARU; FUKUZUMI, YOSHIAKI; AOCHI, HIDEAKI; MATSUOKA, YASUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022828/0882 →
Priority Claims (1)
JP 2008-065882 · Mar 14, 2008 · national
Continuity (1)
Related Publication 20090242967A1 · Oct 1, 2009