Three-dimensional semiconductor memory devices

1. A three-dimensional (3D) semiconductor memory device comprising:

a substrate including a cell array region and a connection region;

an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, and the gate electrodes including electrode pad regions on the connection region;

a first source conductive pattern between the substrate and the electrode structure and on the cell array region;

a lower sacrificial pattern between the substrate and the electrode structure and on the connection region;

a vertical semiconductor pattern penetrating the electrode structure and the first source conductive pattern on the cell array region; and

a dummy vertical semiconductor pattern penetrating one of the electrode pad regions on the connection region,

wherein the lower sacrificial pattern includes a different material from that of the first source conductive pattern.

2. The 3D semiconductor memory device of claim 1 , wherein the vertical semiconductor pattern extends into the substrate.

3. The 3D semiconductor memory device of claim 1 , wherein the first source conductive pattern is in contact with a sidewall of the vertical semiconductor pattern.

4. The 3D semiconductor memory device of claim 3 , further comprising:

a data storage pattern between the vertical semiconductor pattern and the electrode structure,

wherein the data storage pattern is in contact with the first source conductive pattern.

5. The 3D semiconductor memory device of claim 4 , further comprising:

a residual data storage pattern between the vertical semiconductor pattern and the substrate,

wherein the vertical semiconductor pattern is spaced apart from the substrate by the residual data storage pattern.

6. The 3D semiconductor memory device of claim 5 , wherein the data storage pattern is vertically spaced apart from the residual data storage pattern.

7. The 3D semiconductor memory device of claim 1 , wherein the dummy vertical semiconductor pattern is wider, in a second direction parallel to the top surface of the substrate, than the vertical semiconductor pattern.

8. The 3D semiconductor memory device of claim 1 , wherein the dummy vertical semiconductor pattern penetrates the lower sacrificial pattern.

9. The 3D semiconductor memory device of claim 8 , further comprising:

a dummy data storage pattern between the dummy vertical semiconductor pattern and the lower sacrificial pattern.

10. The 3D semiconductor memory device of claim 9 , wherein the dummy vertical semiconductor pattern extends into the substrate, and the dummy data storage pattern extends between the dummy vertical semiconductor pattern and the substrate.

11. The 3D semiconductor memory device of claim 10 , further comprising:

a contact pattern extending from a bottom portion of the dummy vertical semiconductor pattern, penetrating a portion of the dummy data storage pattern, and extending into the substrate.

12. A three-dimensional (3D) semiconductor memory device comprising:

a substrate including a cell array region and a connection region;

an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, the electrode structure extending from the cell array region onto the connection region in a second direction parallel to the top surface of the substrate, and the gate electrodes including electrode pad regions on the connection region;

a source structure between the substrate and the electrode structure, the source structure extending from the cell array region onto the connection region in the second direction;

a lower sacrificial pattern between a first portion of the source structure and the substrate and on the connection region;

a vertical semiconductor pattern penetrating the electrode structure and a second portion of the source structure on the cell array region; and

a dummy vertical semiconductor pattern penetrating one of the electrode pad regions on the connection region,

wherein the dummy vertical semiconductor pattern is wider, in the second direction, than the vertical semiconductor pattern.

13. The 3D semiconductor memory device of claim 12 , wherein the lower sacrificial pattern includes a different material from that of the source structure.

14. The 3D semiconductor memory device of claim 12 ,

wherein the source structure includes a first source conductive pattern between the substrate and the electrode structure and on the cell array region, and

wherein the first source conductive pattern is in contact with a sidewall of the vertical semiconductor pattern.

15. The 3D semiconductor memory device of claim 12 , wherein the vertical semiconductor pattern extends into the substrate.

16. The 3D semiconductor memory device of claim 12 , further comprising:

a data storage pattern between the vertical semiconductor pattern and the electrode structure,

wherein the data storage pattern is in contact with the source structure.

17. The 3D semiconductor memory device of claim 16 , further comprising:

a dummy data storage pattern between the dummy vertical semiconductor pattern and the one of the electrode pad regions,

wherein the dummy data storage pattern is in contact with the first portion of the source structure.

18. The 3D semiconductor memory device of claim 17 , wherein the dummy vertical semiconductor pattern penetrates the lower sacrificial pattern and extends into the substrate.

19. The 3D semiconductor memory device of claim 18 , wherein the dummy data storage pattern extends between the dummy vertical semiconductor pattern and the lower sacrificial pattern and between the dummy vertical semiconductor pattern and the substrate.

20. The 3D semiconductor memory device of claim 19 , further comprising:

a contact pattern extending from a bottom portion of the dummy vertical semiconductor pattern, penetrating a portion of the dummy data storage pattern, and extending into the substrate.