IP Library Granted Patent US 11,036,407
Granted Patent B1
US 11,036,407 · App. 16/888,017 · Granted Jun 15, 2021

Storage system and method for smart folding

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,036,407
App. No.
16/888,017
Granted
Jun 15, 2021
Kind
B1
Abstract

A storage system and method for smart folding are provided. In one example, the storage system has a memory with a plurality of single level cell (SLC) blocks and a multi-level cell (MLC) block. The MLC block has a plurality of pages, each with a different sense time. The storage system tracks a read count of each of the plurality of SLC blocks and determines how to fold the plurality of SLC blocks into the plurality of pages based on the read count of each of the plurality of SLC blocks and the sense time of each of the plurality of pages. In this way, SLC blocks with higher read counts can be folded into pages that have faster sense times.

Claims (28)

1. A storage system comprising:

a memory comprising a plurality of single level cell (SLC) blocks and a multi-level cell (MLC) block, wherein the MLC block comprises a plurality of pages, each with a different sense time; and

a controller configured to:

track a read count of each of the plurality of SLC blocks; and

determine how to fold the plurality of SLC blocks into the plurality of pages based on the read count of each of the plurality of SLC blocks and the sense time of each of the plurality of pages.

2. The storage system of claim 1 , wherein an SLC block with a highest read count is folded into a page in the MLC block that has a fastest sense time.

3. The storage system of claim 1 , wherein the MLC block comprises a quad-level cell (QLC) block.

4. The storage system of claim 3 , wherein the plurality of pages comprise a lower page, a middle page, an upper page, and a top page.

5. The storage system of claim 1 , wherein the controller is further configured to determine when to fold the plurality of SLC blocks into the MLC block.

6. The storage system of claim 1 , wherein the controller is further configured to select the plurality of SLC blocks from an additional plurality of SLC blocks in the memory.

7. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

8. In a storage system comprising a memory comprising a plurality of single level cell (SLC) blocks and a multi-level cell (MLC) block, wherein the MLC block comprises a plurality of pages, each with a different sense time, a method comprising:

determining a number of times each of the plurality of SLC blocks has been read; and

folding the plurality of SLC blocks into the plurality of pages such that an SLC block that had been read more than another SLC block is folded into a page with a faster sense time than a page used to fold the another SLC block.

9. The method of claim 8 , wherein an SLC block that was read a highest number of times is folded into a page in the MLC block that has a fastest sense time.

10. The method of claim 8 , wherein the MLC block comprises a quad-level cell (QLC) block.

11. The method of claim 10 , wherein the plurality of pages comprise a lower page, a middle page, an upper page, and a top page.

12. The method of claim 8 , further comprising determining when to fold the plurality of SLC blocks into the MLC block.

13. The method of claim 8 , further comprising selecting the plurality of SLC blocks from an additional plurality of SLC blocks in the memory.

14. A storage system comprising:

a memory comprising a plurality of single level cell (SLC) blocks and a multi-level cell (MLC) block, wherein the MLC block comprises a plurality of pages, each with a different sense time; and

means for folding the plurality of SLC blocks into the plurality of pages based on how often each of the plurality of SLC blocks was read and the sense time of each of the plurality of pages.

15. The storage system of claim 14 , wherein an SLC block that was read most often is folded into a page in the MLC block that has a fastest sense time.

16. The storage system of claim 14 , wherein the MLC block comprises a quad-level cell (QLC) block.

17. The storage system of claim 16 , wherein the plurality of pages comprise a lower page, a middle page, an upper page, and a top page.

18. The storage system of claim 14 , further comprising means for determining when to fold the plurality of SLC blocks into the MLC block.

19. The storage system of claim 14 , further comprising means for selecting the plurality of SLC blocks from an additional plurality of SLC blocks in the memory.

20. The storage system of claim 14 , wherein the memory comprises a three-dimensional memory.

Assignments (8)
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2020
From: TIKOO, RAKSHIT; NAGHATE, ANKIT; SIKARWAR, YOGENDRA SINGH; THANDAPANI, ARUN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052792/0354 →