IP Library Granted Patent US 11,640,251
Granted Patent B2
US 11,640,251 · App. 17/185,791 · Granted May 2, 2023

Early transition to low power mode for data storage devices

Inventors: Shay Benisty (Beer Sheva, IL); Judah Gamliel Hahn (Ofra, IL); Ariel Navon (Revava, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0625G06F3/0629G06F3/0634G06F3/0653G06F3/0679
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Quick Facts
Patent No.
US 11,640,251
App. No.
17/185,791
Granted
May 2, 2023
Kind
B2
Abstract

The present disclosure generally relates to data storage devices, such as solid state drives, and effective power management of the data storage device. The data storage device includes a controller, where the controller is configured to predict when a host device will send a command to enter a low power state, prepare the data storage device to enter the low power state, and receive a command to enter the low power state after the predicting and preparing. If the data storage device is idled for greater than a threshold value, then the data storage device prepares to transition to a low power state but will wait to enter the lower power state until receiving a request from a host device.

Claims (51)

1. A data storage device, comprising:

a non-volatile memory device; and

a controller coupled to the non-volatile memory device, wherein the controller is configured to:

predict when a host device will send a command to enter a low power state, wherein the predicting comprises calculating, based on a history of previous idle time timeouts, a recommended idle time threshold and a calculated confidence threshold;

prepare the data storage device to enter the low power state, wherein the preparing is based on reaching the recommended idle time threshold and determining that a confidence level for entering the lower power state is greater than or equal to the calculated confidence threshold, wherein the preparing comprises performing one or more low power state transition processes prior to receiving the command to enter the low power state, wherein the one or more low power state transition processes performed prior to receiving the command to enter the low power state comprise at least one of:

flushing all cached data to the non-volatile memory device;

copying required content from at least one of a required memory and a register to the non-volatile memory device; and

placing dynamic random access memory (DRAM) located in the controller into a refresh mode;

receive the command to enter the low power state after the predicting and the preparing; and

enter the low power state responsive to receiving the command to enter the low power state.

2. The data storage device of claim 1 , wherein the predicting further comprises:

determining that the data storage device is not busy with input/output commands; and

activating a timer.

3. The data storage device of claim 2 , wherein the predicting further comprises:

calculating whether the timer has a value that is greater than the calculated confidence threshold.

4. The data storage device of claim 3 , wherein the controller is further configured to recalculate the calculated confidence threshold after receiving the command to enter the low power state.

5. The data storage device of claim 1 , wherein the calculated confidence threshold is calculated by analyzing the history of previous idle time timeouts and correlating the previous idle time timeouts to additional host signals.

6. The data storage device of claim 5 , wherein the additional host signals comprise a non-operational power state permissive mode enable signal.

7. The data storage device of claim 6 , wherein the controller is further configured to:

calculate a recommended idle time threshold and confidence level; and

determine if a calculated confidence level is sufficient to trigger an early transition to the lower power state.

8. The data storage device of claim 1 , wherein the controller is configured to place the data storage device into the low power state upon calculating an updated calculated confidence threshold.

9. A data storage device, comprising:

a non-volatile memory device; and

a controller coupled to the non-volatile memory device, wherein the controller is configured to:

analyze a history of previous idle timeouts where a host device issued a command for the data storage device to enter a low power state;

correlate the previous idle timeouts to other host device signals;

calculate a recommended idle time threshold based upon the history and the correlating;

calculate a confidence level based upon the history and the correlating;

determine whether the calculated confidence level is sufficient to trigger an early transition to a low power state, wherein triggering the early transition to the low power state comprises performing one or more low power state transition processes prior to receiving the command to enter the low power state; wherein the one or more low power state transition processes performed prior to receiving the command to enter the low power state comprise at least one of:

flushing all cached data to the non-volatile memory device;

copying required content from at least one of a required memory and a register to the non-volatile memory device; and

placing dynamic random access memory (DRAM) that is located in the controller into a refresh mode;

receive the command to enter the low power state; and

enter the low power state responsive to receiving the command to enter the low power state.

10. The data storage device of claim 9 , wherein the controller is configured to set a low power state threshold to 0 upon determining that the calculated confidence level is not sufficient to trigger an early transition to the low power state.

11. The data storage device of claim 9 , wherein the controller is configured to set a low power state threshold to the recommended idle time threshold upon determining that the calculated confidence level is sufficient to trigger an early transition to the low power state.

12. The data storage device of claim 9 , wherein the controller is configured to perform the one or more low power state transition processes performed prior to receiving the command to enter the low power state upon determining the calculated confidence level is sufficient to trigger the early transition to the low power state.

13. A data storage device, comprising:

memory means;

means to prepare the data storage device to enter a low power state prior to receiving an instruction from a host device to enter the low power state, wherein:

preparing the data storage device is based on reaching a recommended idle time threshold and determining whether a confidence level for entering the lower power state is greater than or equal to a calculated confidence threshold;

the recommended idle time threshold and the calculated confidence threshold are based on a history of idle time timeouts; and

preparing the data storage device comprises performing one or more low power state transition processes prior to receiving the instruction to enter the low power state, wherein the one or more low power state transition processes performed prior to receiving the instruction to enter the low power state comprise at least one of:

flushing all cached data to the memory means;

copying required content from at least one of a required memory and a register to the memory means; and

placing dynamic random access memory (DRAM) that is located in the controller into a refresh mode;

means to estimate the confidence level for entering the low power state, wherein the means to prepare operates based upon the means to estimate; and

means to enter the low power state responsive to receiving the instruction to enter the low power state, wherein the memory means is coupled to the means to prepare, the means to estimate, and the means to enter.

14. The data storage device of claim 13 , further comprising a timer that is activated when the data storage device is not busy with input or output commands.

15. The data storage device of claim 14 , wherein the means to prepare operates when the timer has a value greater than a value provided by the means to estimate.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2021
From: BENISTY, SHAY; HAHN, JUDAH GAMLIEL; NAVON, ARIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055431/0522 →